Digit serial data transmission can be used to an advantage in the design of special purpose processors where communication issues dominate and where digit pipelining can be used to maintain high data rates. VLSI signal processing is one such problem domain. We propose detailed designs of unidirectional systolic and semisystolic programmable digit pipelined (serial) multipliers. These multipliers are programmable; i.e., one operand is prestored in the multiplier and the other operand is fed in a digit serial fashion. The VLSI implementation of the systolic multiplier is given. This systolic multiplier is used in our VLSI signal processing system. Lastly, for the sake of completeness we also propose designs of nonprogrammable unidirectional and bidirectional digit serial multipliers.
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture
- Computer Networks and Communications
- Artificial Intelligence