TY - JOUR
T1 - Distributed parametric resonator
T2 - A passive CMOS frequency divider
AU - Lee, Wooram
AU - Afshari, Ehsan
N1 - Funding Information:
Manuscript received December 07, 2009; revised May 21, 2010; accepted May 29, 2010. Date of current version August 25, 2010. This paper was approved by Associate Editor Jacques Rudell. This work was supported in part by the C2S2 Focus Center, one of six research centers funded under the Focus Center Research Program (FCRP), a Semiconductor Research Corporation entity, and also by the National Science Foundation under CAREER Award 0954537. The work of W. Lee was supported by a Samsung fellowship.
PY - 2010/9
Y1 - 2010/9
N2 - We present an electrical distributed parametric oscillator to realize a passive CMOS frequency divider with low phase noise. Instead of using active devices, which are the main sources of noise and power consumption, an oscillation at half of the input frequency is sustained by the parametric process based on nonlinear interaction with the input signal. To show the feasibility of the proposed approach, we have implemented a 20-GHz frequency divider in a 0.13-μm CMOS process. Without any dc power consumption, 600-mV differential output amplitude is achieved for an input amplitude of 600 mV. The input frequency ranges from 18.5 to 23.5 GHz with varactor tuning. The output phase noise is almost 6 dB lower than that of the input signal for all offset frequencies up to 1 MHz. There is a good agreement among analysis, simulation, and 10-MHz measurement results. To the best of our knowledge, this is the first passive frequency divider in a CMOS process.
AB - We present an electrical distributed parametric oscillator to realize a passive CMOS frequency divider with low phase noise. Instead of using active devices, which are the main sources of noise and power consumption, an oscillation at half of the input frequency is sustained by the parametric process based on nonlinear interaction with the input signal. To show the feasibility of the proposed approach, we have implemented a 20-GHz frequency divider in a 0.13-μm CMOS process. Without any dc power consumption, 600-mV differential output amplitude is achieved for an input amplitude of 600 mV. The input frequency ranges from 18.5 to 23.5 GHz with varactor tuning. The output phase noise is almost 6 dB lower than that of the input signal for all offset frequencies up to 1 MHz. There is a good agreement among analysis, simulation, and 10-MHz measurement results. To the best of our knowledge, this is the first passive frequency divider in a CMOS process.
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U2 - 10.1109/JSSC.2010.2056833
DO - 10.1109/JSSC.2010.2056833
M3 - Article
AN - SCOPUS:77956196112
SN - 0018-9200
VL - 45
SP - 1834
EP - 1844
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 9
M1 - 5556456
ER -