Do chip size limits exist for DCA?

Andreas Schubert, Rainer Dudek, Rudolf Leutenbauer, Ralf Döring, Joachim Kloeser, H. Oppermann, Bernd Michel, Herbert Reichl, Daniel F. Baldwin, Jianmin Qu, Suresh K. Sitaraman, Madhavan Swaminathan, C. P. Wong, Rao Tummala

Research output: Contribution to journalArticlepeer-review

8 Scopus citations


Solder joints, the most widely used flip chip on board (FCOB) interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. The coefficient of thermal expansion (CTE) of the printed wiring board (PWB) is almost an order of magnitude greater than that of the integrated circuit (IC). Under operating and testing conditions, this mismatch subjects the solder joints to large creep strains and leads to early failure of the solder connections. The reliability of such flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate together to locally constrain the CTE mismatch. However, the effects of CTE mismatch are assumed to become more severe with increasing chip size. Even with the addition of an underfill material, it has been supposed that there are limits on the chip size used in flip chip applications.

Original languageEnglish (US)
Pages (from-to)255-263
Number of pages9
JournalIEEE Transactions on Electronics Packaging Manufacturing
Issue number4
StatePublished - 1999

All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering


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