Do chip size limits exist for DCA?

A. Schubert, R. Dudek, R. Leutenbauer, R. Döring, J. Kloeser, H. Oppermann, B. Michel, H. Reichl, D. Baldwin, J. Qu, S. Sitaraman, M. Swaminathan, C. P. Wong, R. Tummala

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations


Solder joints, the most widely used flip chip on board (FCOB) interconnects, have relatively low structural compliance due to the large thermal expansion mismatch between Si die and organic substrate. The PWB CTE is almost an order of magnitude greater than that of the IC. Under operating and testing conditions, this mismatch subjects solder joints to large creep strains and leads to early solder joint failure. FCOB structure reliability can be enhanced by applying an epoxy-based underfill between chip and substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate to constrain the CTE mismatch locally. However, CTE mismatch effects are assumed to become more severe with increasing chip size. Even with the use of underfill, it is supposed that there are limits on chip size in flip chip applications. Fraunhofer Institute IZM/Technical University are collaborating with Georgia Tech to study fundamental limits of direct chip attach. The objectives are: to understand material and mechanical issues related to thermo-mechanical reliability of direct chip attach; to determine fundamental chip size limits by taking process conditions, process-induced defects, underfill material property requirements, geometry limitations and service environment into consideration; to investigate the impact of geometrical, material and operating parameters on FCOB assembly thermomechanical reliability and to determine an optimum combination of parameters to minimize delamination, solder joint fatigue, chip cracking and/or excessive warpage; to validate FEA simulations experimentally.

Original languageEnglish (US)
Title of host publicationProceedings - International Symposium on Advanced Packaging Materials
Subtitle of host publicationProcesses, Properties and Interfaces
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages8
ISBN (Electronic)0930815564, 9780930815561
StatePublished - 1999
Event1999 International Symposium on Advanced Packaging Materials - Braselton, United States
Duration: Mar 14 1999Mar 17 1999

Publication series

NameProceedings - International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces


Conference1999 International Symposium on Advanced Packaging Materials
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Polymers and Plastics


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