TY - GEN
T1 - Do we need wide flits in Networks-on-Chip?
AU - Lee, Junghee
AU - Nicopoulos, Chrysostomos
AU - Park, Sung Joo
AU - Swaminathan, Madhavan
AU - Kim, Jongman
PY - 2013
Y1 - 2013
N2 - Packet-based Networks-on-Chip (NoC) have emerged as the most viable candidates for the interconnect backbone of future Chip Multi-Processors (CMP). The flit size (or width) is one of the fundamental design parameters within a NoC router, which affects both the performance and the cost of the network. Most studies pertaining to the NoC of general-purpose microprocessors adopt a certain flit width without any reasoning or explanation. In fact, it is not easy to pinpoint an optimal flit size, because the flit size is intricately intertwined with various aspects of the system. This paper aims to provide a guideline on how to choose an appropriate flit width. It will be demonstrated that arbitrarily choosing a flit width without proper investigation may have serious repercussions on the overall behavior of the system.
AB - Packet-based Networks-on-Chip (NoC) have emerged as the most viable candidates for the interconnect backbone of future Chip Multi-Processors (CMP). The flit size (or width) is one of the fundamental design parameters within a NoC router, which affects both the performance and the cost of the network. Most studies pertaining to the NoC of general-purpose microprocessors adopt a certain flit width without any reasoning or explanation. In fact, it is not easy to pinpoint an optimal flit size, because the flit size is intricately intertwined with various aspects of the system. This paper aims to provide a guideline on how to choose an appropriate flit width. It will be demonstrated that arbitrarily choosing a flit width without proper investigation may have serious repercussions on the overall behavior of the system.
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U2 - 10.1109/ISVLSI.2013.6654614
DO - 10.1109/ISVLSI.2013.6654614
M3 - Conference contribution
AN - SCOPUS:84893557443
SN - 9781479913312
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 2
EP - 7
BT - Proceedings - 2013 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013
PB - IEEE Computer Society
T2 - 2013 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013
Y2 - 5 August 2013 through 7 August 2013
ER -