Domain Wall Memory based Digital Signal processors for area and energy-efficiency

Jinil Chung; Kenneth Ramclam; Jongsun Park; Swaroop Ghosh

doi:10.1145/2744769.2744825

Domain Wall Memory based Digital Signal processors for area and energy-efficiency

Jinil Chung
, Kenneth Ramclam
, Jongsun Park
, Swaroop Ghosh

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

In many Digital Signal Processing (DSP) applications such as Viterbi decoder and Fast Fourier Transform (FFT), Static Random Access Memory (SRAM) based embedded memory consumes significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory is inefficient in terms of area and power. We propose spintronic Domain Wall Memory (DWM) based embedded memories for DSP building blocks e.g., survivor-path memories in Viterbi decoder and First-In-First-Out (FIFO) register files in FFT processor that exploit the unique serial access mechanism, non-volatility and small footprint of the memory for area and power saving. Simulations using 65nm technology show that the DWM based Viterbi decoder achieves 66.4 % area and 59.6 % power savings over the conventional SRAM-based implementation. For 8K point FFT processor, the DWM based design shows 60.6 % area and 60.3 % power savings.

Original language	English (US)
Title of host publication	2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781450335201
DOIs	https://doi.org/10.1145/2744769.2744825
State	Published - Jul 24 2015
Event	52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 - San Francisco, United States Duration: Jun 7 2015 → Jun 11 2015

Publication series

Name	Proceedings - Design Automation Conference
Volume	2015-July
ISSN (Print)	0738-100X

Other

Other	52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
Country/Territory	United States
City	San Francisco
Period	6/7/15 → 6/11/15

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modeling and Simulation

Access to Document

10.1145/2744769.2744825

Cite this

Chung, J., Ramclam, K., Park, J., & Ghosh, S. (2015). Domain Wall Memory based Digital Signal processors for area and energy-efficiency. In 2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 Article 7167248 (Proceedings - Design Automation Conference; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2744769.2744825

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title = "Domain Wall Memory based Digital Signal processors for area and energy-efficiency",

abstract = "In many Digital Signal Processing (DSP) applications such as Viterbi decoder and Fast Fourier Transform (FFT), Static Random Access Memory (SRAM) based embedded memory consumes significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory is inefficient in terms of area and power. We propose spintronic Domain Wall Memory (DWM) based embedded memories for DSP building blocks e.g., survivor-path memories in Viterbi decoder and First-In-First-Out (FIFO) register files in FFT processor that exploit the unique serial access mechanism, non-volatility and small footprint of the memory for area and power saving. Simulations using 65nm technology show that the DWM based Viterbi decoder achieves 66.4 \% area and 59.6 \% power savings over the conventional SRAM-based implementation. For 8K point FFT processor, the DWM based design shows 60.6 \% area and 60.3 \% power savings.",

author = "Jinil Chung and Kenneth Ramclam and Jongsun Park and Swaroop Ghosh",

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Chung, J, Ramclam, K, Park, J & Ghosh, S 2015, Domain Wall Memory based Digital Signal processors for area and energy-efficiency. in 2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015., 7167248, Proceedings - Design Automation Conference, vol. 2015-July, Institute of Electrical and Electronics Engineers Inc., 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015, San Francisco, United States, 6/7/15. https://doi.org/10.1145/2744769.2744825

Domain Wall Memory based Digital Signal processors for area and energy-efficiency. / Chung, Jinil; Ramclam, Kenneth; Park, Jongsun et al.
2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7167248 (Proceedings - Design Automation Conference; Vol. 2015-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Domain Wall Memory based Digital Signal processors for area and energy-efficiency

AU - Chung, Jinil

AU - Ramclam, Kenneth

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Y1 - 2015/7/24

N2 - In many Digital Signal Processing (DSP) applications such as Viterbi decoder and Fast Fourier Transform (FFT), Static Random Access Memory (SRAM) based embedded memory consumes significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory is inefficient in terms of area and power. We propose spintronic Domain Wall Memory (DWM) based embedded memories for DSP building blocks e.g., survivor-path memories in Viterbi decoder and First-In-First-Out (FIFO) register files in FFT processor that exploit the unique serial access mechanism, non-volatility and small footprint of the memory for area and power saving. Simulations using 65nm technology show that the DWM based Viterbi decoder achieves 66.4 % area and 59.6 % power savings over the conventional SRAM-based implementation. For 8K point FFT processor, the DWM based design shows 60.6 % area and 60.3 % power savings.

AB - In many Digital Signal Processing (DSP) applications such as Viterbi decoder and Fast Fourier Transform (FFT), Static Random Access Memory (SRAM) based embedded memory consumes significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory is inefficient in terms of area and power. We propose spintronic Domain Wall Memory (DWM) based embedded memories for DSP building blocks e.g., survivor-path memories in Viterbi decoder and First-In-First-Out (FIFO) register files in FFT processor that exploit the unique serial access mechanism, non-volatility and small footprint of the memory for area and power saving. Simulations using 65nm technology show that the DWM based Viterbi decoder achieves 66.4 % area and 59.6 % power savings over the conventional SRAM-based implementation. For 8K point FFT processor, the DWM based design shows 60.6 % area and 60.3 % power savings.

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M3 - Conference contribution

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ER -

Domain Wall Memory based Digital Signal processors for area and energy-efficiency

Abstract

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UN SDGs

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