Double-Gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM

Ashish Goel, Sumeet Gupta, Aditya Bansal, Meng Hsueh Chiang, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Over the past few decades, CMOS technology has mainly been driven by transistor scaling. However, the scaling benefits of conventional bulk MOSFETs come at the cost of increased short channel effects, degrading their performance as a switch. In order to counter such effects, device structures with enhanced gate control of the channel have been proposed [1]. A double-gate (DG) MOSFET is one such structure which has shown tremendous promise. Due to reduced junction capacitance in DG-MOSFETs, drain capacitance is mainly dominated by the overlap capacitance, which may be reduced by introducing an underlap between source/drain and channel. However, underlap on the source side leads to significant degradation in ON-current as well as increased effect of process variations on the threshold voltage. Hence, in this paper, we explore the design and optimization of DG-MOSFETs with underlap only on the drain side.

Original languageEnglish (US)
Title of host publication67th Device Research Conference, DRC 2009
Pages57-58
Number of pages2
DOIs
StatePublished - Dec 11 2009
Event67th Device Research Conference, DRC 2009 - University Park, PA, United States
Duration: Jun 22 2009Jun 24 2009

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770

Other

Other67th Device Research Conference, DRC 2009
Country/TerritoryUnited States
CityUniversity Park, PA
Period6/22/096/24/09

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Double-Gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM'. Together they form a unique fingerprint.

Cite this