DR-SNUCA: An energy-scalable dynamically partitioned cache

Anshuman Gupta, Jack Sampson, Michael Bedford Taylor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Multicore processors have become ubiquitous across many domains, such as datacenters and smartphones. As the number of processing elements increases within these processors, so does the pressure to share the critical on-chip cache resources, but this must be done energy-efficiently and without sacrificing resource guarantees. We propose a scalable dynamic cache-partitioning scheme, DR-SNUCA, which provides an energy-efficient way to reduce resource interference over caches shared among many processing elements. Our results show that DR-SNUCA reduces system energy consumption by 16.3% compared to associatively partitioned caches, such as DNUCA.

Original languageEnglish (US)
Title of host publication2013 IEEE 31st International Conference on Computer Design, ICCD 2013
PublisherIEEE Computer Society
Pages515-518
Number of pages4
ISBN (Print)9781479929870
DOIs
StatePublished - 2013
Event2013 IEEE 31st International Conference on Computer Design, ICCD 2013 - Asheville, NC, United States
Duration: Oct 6 2013Oct 9 2013

Publication series

Name2013 IEEE 31st International Conference on Computer Design, ICCD 2013

Other

Other2013 IEEE 31st International Conference on Computer Design, ICCD 2013
Country/TerritoryUnited States
CityAsheville, NC
Period10/6/1310/9/13

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture

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