TY - GEN
T1 - Drain-offset ZnO thin film transistors for high voltage operations
AU - Gong, Yiyang
AU - Jackson, Thomas N.
PY - 2016/8/22
Y1 - 2016/8/22
N2 - We report ZnO thin film transistors (TFTs) with offset drain for high voltage operation. Offset-drain FETs using Si, a-Si:H, and pentacene have been previously demonstrated [1,2,3]. The TFTs use a bottom gate structure with Al2O3 gate dielectric and ZnO active layers deposited by plasma enhanced atomic layer deposition (PEALD). As the drain offset is increased from 0 μm to 2 μm· the drain-to-source breakdown voltage increased from 33 V to 82 V, while the linear mobility decreased from 10 cm2/Vs to 4 cm2/Vs. Our process flow is simple and compatible with glass and polymeric substrates.
AB - We report ZnO thin film transistors (TFTs) with offset drain for high voltage operation. Offset-drain FETs using Si, a-Si:H, and pentacene have been previously demonstrated [1,2,3]. The TFTs use a bottom gate structure with Al2O3 gate dielectric and ZnO active layers deposited by plasma enhanced atomic layer deposition (PEALD). As the drain offset is increased from 0 μm to 2 μm· the drain-to-source breakdown voltage increased from 33 V to 82 V, while the linear mobility decreased from 10 cm2/Vs to 4 cm2/Vs. Our process flow is simple and compatible with glass and polymeric substrates.
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U2 - 10.1109/DRC.2016.7548469
DO - 10.1109/DRC.2016.7548469
M3 - Conference contribution
AN - SCOPUS:84987707863
T3 - Device Research Conference - Conference Digest, DRC
BT - 74th Annual Device Research Conference, DRC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 74th Annual Device Research Conference, DRC 2016
Y2 - 19 June 2016 through 22 June 2016
ER -