TY - GEN
T1 - Dynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile
AU - Ma, Kaisheng
AU - Li, Xueqing
AU - Liu, Yongpan
AU - Sampson, John
AU - Xie, Yuan
AU - Narayanan, Vijaykrishnan
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/1/5
Y1 - 2016/1/5
N2 - Energy harvesting systems without an energy storage device have to efficiently harness the fluctuating and weak power sources to ensure the maximum computational progress. While a simpler processor enables a higher turn-on potential with a weak source, a more powerful processor can utilize more energy that is harvested. Earlier work shows that different complexity levels of nonvolatile microarchitectures provide best fit for different power sources, and even different trails within same power source. In this work, we propose a dynamic nonvolatile microarchitecture by integrating all non-pipelined (NP), N-stage-pipeline (NSP), and Out of Order (OoO) cores together. Neural network machine learning algorithms are also integrated to dynamically adjust the microarchitecture to achieve the maximum forward progress. This integrated solution can achieve forward progress equal to 2.4× of the baseline NP architecture (1.82× of an OoO core).
AB - Energy harvesting systems without an energy storage device have to efficiently harness the fluctuating and weak power sources to ensure the maximum computational progress. While a simpler processor enables a higher turn-on potential with a weak source, a more powerful processor can utilize more energy that is harvested. Earlier work shows that different complexity levels of nonvolatile microarchitectures provide best fit for different power sources, and even different trails within same power source. In this work, we propose a dynamic nonvolatile microarchitecture by integrating all non-pipelined (NP), N-stage-pipeline (NSP), and Out of Order (OoO) cores together. Neural network machine learning algorithms are also integrated to dynamically adjust the microarchitecture to achieve the maximum forward progress. This integrated solution can achieve forward progress equal to 2.4× of the baseline NP architecture (1.82× of an OoO core).
UR - http://www.scopus.com/inward/record.url?scp=84964506908&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84964506908&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.2015.7372634
DO - 10.1109/ICCAD.2015.7372634
M3 - Conference contribution
AN - SCOPUS:84964506908
T3 - 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
SP - 670
EP - 675
BT - 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
Y2 - 2 November 2015 through 6 November 2015
ER -