Dynamic reconfigurable networks in NoC for I/O supported parallel applications

Keyphrases

• Parallel Applications 100%
• Network on chip 100%
• In-network 100%
• Network Reconfiguration 100%
• Chip Area 50%
• Dynamic Reconfiguration 50%
• Adapter 25%
• Silica Substrate 25%
• Motivation 25%
• Power Consumption 25%
• Reconfiguration 25%
• Chip multiprocessor 25%
• Die Area 25%
• Promising Solutions 25%
• On chip 25%
• Communication Efficiency 25%
• Manufacturing Technology 25%
• Communication Patterns 25%
• Processing Element 25%
• Communication Infrastructure 25%
• Network Communication 25%
• On-chip Interconnects 25%
• Many-core 25%
• On-chip Structure 25%
• Regionalized 25%
• Network-on-chip Architectures 25%

Computer Science

• Input/Output 100%
• Parallel Application 100%
• Networks on Chips 100%
• Reconfigurable Network 100%
• Dynamic Reconfiguration 40%
• Experimental Result 20%
• Power Consumption 20%
• Chip Multiprocessor 20%
• Communication Network 20%
• Processing Element 20%
• Chip Architecture 20%
• Many-Core 20%

Engineering

• Network-on-Chip 100%
• Chip Area 66%
• Dynamic Reconfiguration 66%
• Nodes 33%
• Experimental Result 33%
• Electric Power Utilization 33%
• Manufacturing Engineering 33%
• Communication Infrastructure 33%
• Chip Architecture 33%
• Silicon Dioxide 33%
• Processing Element 33%