TY - GEN
T1 - Effect of distributed directories in mesh interconnects
AU - Horro, Marcos
AU - Kandemir, Mahmut T.
AU - Pouchet, Louis Noël
AU - Rodríguez, Gabriel
AU - Touriño, Juan
N1 - Funding Information:
This work was supported in part by the Ministry of Economy, Industry and Competitiveness of Spain (TIN2016-75845-P AEI/FED-ER/EU), by the Ministry of Education (FPU16/00816), and by the U.S. National Science Foundation award CCF-1750399.
Publisher Copyright:
© 2019 Copyright held by the owner/author(s). Publication rights licensed to ACM.
PY - 2019/6/2
Y1 - 2019/6/2
N2 - Recent manycore processors are kept coherent using scalable distributed directories. A paramount example is the Xeon Phi Knights Landing. It features 38 tiles packed in a single die, organized into a 2D mesh. Before accessing remote data, tiles need to query the distributed directory. The effect of this coherence traffic is poorly understood.We show that the apparent UMA behavior results from the degradation of the peak performance. We develop ways to optimize the coherence traffic, the core-to-core-affinity, and the scheduling of a set of tasks on the mesh, leveraging the unique characteristics of processor units stemming from process variations.
AB - Recent manycore processors are kept coherent using scalable distributed directories. A paramount example is the Xeon Phi Knights Landing. It features 38 tiles packed in a single die, organized into a 2D mesh. Before accessing remote data, tiles need to query the distributed directory. The effect of this coherence traffic is poorly understood.We show that the apparent UMA behavior results from the degradation of the peak performance. We develop ways to optimize the coherence traffic, the core-to-core-affinity, and the scheduling of a set of tasks on the mesh, leveraging the unique characteristics of processor units stemming from process variations.
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U2 - 10.1145/3316781.3317808
DO - 10.1145/3316781.3317808
M3 - Conference contribution
AN - SCOPUS:85067824909
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 56th Annual Design Automation Conference, DAC 2019
Y2 - 2 June 2019 through 6 June 2019
ER -