Effect of light illumination on threshold voltage and sub-threshold slope of amorphous silicon thin film transistors

In this study the light induced defect state creation under 1 sun illumination is investigated through changes in sub-threshold slope, Δ, and threshold voltage, V_T, in a-Si:H TFT structures. Threshold voltage changes can be due to either charge trapping or defect state creation near the interface of gate insulator and a-Si:H active layer. The charge trapping effects have been minimized by incorporating high quality thermal silicon dioxide in the a-Si:H TFT, and the changes in threshold voltage can be attributed to induced defect states in the a-Si:H. Since the sub-threshold current is closely related to the band gap defect states, both V_T and Δ can be used as a new probe to study the light induced defect creation in the a-Si:H. The information obtained about the nature of gap defect states from the analysis of changes in V_T and Δ under light illumination is presented. The results obtained show that under 1 sun illumination there are very fast increases (within 10 seconds) in V_T with subsequent slow increases and no observable changes in Δ, similar to those observed in the light induced photoconductivity changes in a-Si:H thin films. Results are also presented on changes in V_T under gate-bias stress. Comparisons are then made between the results obtained under 1 sun light illumination and those under gate-bias stress. The information obtained in this study about the nature of the gap defect states derived from characterization of the sub-threshold regimes is discussed.