Effect of Plasma Etching Edge-Type Exposures on Si Substrates: A Correlation Between Carrier Lifetime and Etch-Induced Defect States

Recently there has been increasing evidence that poly-Si gate reactive ion etching produces gate SiO₂ edge damage in MOS transistors in addition to the well-known areal plasma charging stress damage. This edge damage is believed to be due to direct exposure of these regions to plasma photon and particle fluxes. To explore this edge type damage further, the effect of this direct exposure on Si substrate is studied using blanket SiO₂/Si structures subjected to poly-Si overetches. These'structures were then characterized using capacitance-voltage and deep level transient spectroscopy measurements. Defect states are found in the Si substrate and at the SiO₂/Si interface after this type of overetch exposure. Their presence is shown to correlate with the degradation of the minority carrier generation lifetime and surface generation velocity observed by Zerbst measurements.