Efficient VLSI implementation of inverse discrete cosine transform

In this paper, a novel 2-D IDCT architecture based on the energy compaction property of 2-D DCT is proposed. This architecture performs 2-D IDCT directly on the 2-D DCT data set, avoiding the need for the transposition memory. We derive a recursion equation from the definition of the 2-D IDCT algorithm and use it to implement a wavefront array processor. The wavefront array processor consists of highly regular, parallel and pipelined processing elements which are suitable for VLSI implementation. This implementation also utilizes the sparseness property of the 2-D DCT coefficients to reduce the computational complexity. It is shown that the proposed architecture achieves a high throughput rate, (15 + m) clock cycles per 2-D DCT data set, where m is the number of the non-zero DCT coefficients. Another important aspect of this architecture is that it provides an efficient way to control the trade-off between visual quality of the reconstructed image and computational complexity.