Electrical design and modeling challenges for 3D system integration

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations


Over the last several years, the buzzword in the electronics industry has been "More than Moore", referring to the embedding of components into the package substrate and stacking of ICs and packages using wirebond and package on package (POP) technologies. This has led to the development of technologies that can lead to the ultra-miniaturization of electronic systems with coining of terms such as SIP (System in Package) and SOP (System on Package). More recently, the semiconductor industry has started focusing more on 3D integration using Through Silicon Vias (TSV). This is being quoted as a revolution in the electronics industry by several leading technologists. 3D technology, an alternative solution to the scaling problems being faced by the semiconductor industry provides a 3rd dimension for connecting transistors, ICs and packages together with short interconnections, with the possibility for miniaturization, as never before. The semiconductor industry is investing heavily on TSVs as it provides opportunities for improved performance, bandwidth, lower power, reduced delay, lower cost and overall system miniaturization. Interposers play a very important role in such 3D integrated systems since they act as the conduit for supplying power, interfacing to the external world and handling the thermal management for 3D IC stacks. Two different technologies are being proposed for the interposer today namely, silicon and glass. Though glass provides a low loss substrate solution it has its disadvantages which can be corrected using silicon. Similarly, silicon has several performance advantages but is limited due to the semiconductor properties of the substrate which can be corrected using glass. So, which provides a better alternative from an electrical performance standpoint - silicon or glass? In this paper, the electrical design and modeling challenges associated with 3D integration using TSVs is discussed with primary focus on the interposer. The results are contrasted with a glass interposer solution.

Original languageEnglish (US)
Title of host publicationDesignCon 2012
Subtitle of host publicationWhere Chipheads Connect
Number of pages93
StatePublished - 2012
EventDesignCon 2012: Where Chipheads Connect - Santa Clara, CA, United States
Duration: Jan 30 2012Feb 2 2012

Publication series

NameDesignCon 2012: Where Chipheads Connect


OtherDesignCon 2012: Where Chipheads Connect
Country/TerritoryUnited States
CitySanta Clara, CA

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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