Electrical design of wafer level package on board for gigabit data transmission

W. Kim, R. Madhavan, J. Mao, J. Choi, S. Choi, D. Ravi, V. Sundaram, S. Sankararaman, P. Gupta, Z. Zhang, G. Lo, M. Swaminathan, R. Tummala, S. Sitaraman, C. P. Wong, M. Iyer, M. Rotaru, A. Tay

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations


This paper discusses the design of a wafer level package on board for 5GHz data transmission. The design is based on the 2005 node of the International Technology Roadmap on Semiconductors (ITRS) that predicts a clock frequency of 5GHz, power of 170W and an operating voltage of 0.9V for high-end microprocessors. The goal of this paper is to demonstrate the ability to support global interconnections on the board at a speed comparable to the clock frequency and supply adequate power to the chip. This requires careful design of the topology of the interconnections, control of the eddy current losses in Silicon, control of the conductor and dielectric losses in the board and design of the transition between the chip and the board. The electrical design process is discussed in detail using a test vehicle, in this paper. The test vehicle consists of Co-planar waveguide (CPW) lines on high resistivity Silicon Substrate connected to CPW lines on low k, low loss board. The transition between the chip and board is completed through solder bumps with 50 μm diameter and 100 μm pitch. Both the Silicon and Board transmission lines have been characterized using TDR measurements. In addition, the inductance of the solder bumps have been extracted. Using synthesized models extracted from measurements, the eye diagrams for 5GHz data transmission has been simulated to show the importance of losses for 1mm long Silicon lines connected to 5cm long board lines through low inductance solder bumps. In addition, the effect of underfill and curing on signal propagation have been quantified.

Original languageEnglish (US)
Title of host publicationProceedings of 5th Electronics Packaging Technology Conference, EPTC 2003
EditorsMahadevan K. Iyer, Yew Cheong Mui, Kok Chuan Toh
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages10
ISBN (Electronic)0780382056, 9780780382053
StatePublished - 2003
Event5th Electronics Packaging Technology Conference, EPTC 2003 - Singapore, Singapore
Duration: Dec 10 2003Dec 12 2003

Publication series

NameProceedings of 5th Electronics Packaging Technology Conference, EPTC 2003


Conference5th Electronics Packaging Technology Conference, EPTC 2003

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Electronic, Optical and Magnetic Materials


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