TY - GEN
T1 - Electrical modeling of through silicon and package vias
AU - Bandyopadhyay, Tapobrata
AU - Chatterjee, Ritwik
AU - Chung, Daehyun
AU - Swaminathan, Madhavan
AU - Tummala, Rao
PY - 2009
Y1 - 2009
N2 - This paper presents analytical modeling and 3D full-wave electromagnetic (EM) simulation of the bias voltage dependent semiconductor (MOS) capacitance of a Through Silicon Via (TSV). An accurate electrical model of the TSV is proposed by considering the semiconductor effects. The highfrequency electrical performance of TSVs and Through-Package Vias (TPVs) are compared by means of 3D EM simulations. A parametric study is performed on TSV capacitance and design guidelines are presented for signal and power TSVs.
AB - This paper presents analytical modeling and 3D full-wave electromagnetic (EM) simulation of the bias voltage dependent semiconductor (MOS) capacitance of a Through Silicon Via (TSV). An accurate electrical model of the TSV is proposed by considering the semiconductor effects. The highfrequency electrical performance of TSVs and Through-Package Vias (TPVs) are compared by means of 3D EM simulations. A parametric study is performed on TSV capacitance and design guidelines are presented for signal and power TSVs.
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U2 - 10.1109/3DIC.2009.5306542
DO - 10.1109/3DIC.2009.5306542
M3 - Conference contribution
AN - SCOPUS:70549111064
SN - 9781424445127
T3 - 2009 IEEE International Conference on 3D System Integration, 3DIC 2009
BT - 2009 IEEE International Conference on 3D System Integration, 3DIC 2009
T2 - 2009 IEEE International Conference on 3D System Integration, 3DIC 2009
Y2 - 28 September 2009 through 30 September 2009
ER -