Electrical properties of p- and n-type silicon nanowires

Yanfeng Wang; Marco Cabassi; Tsung Ta Ho; Kok Keong Lew; Joan Redwing; Theresa Mayer

doi:10.1109/DRC.2004.1367764

Electrical properties of p- and n-type silicon nanowires

Yanfeng Wang, Marco Cabassi, Tsung Ta Ho, Kok Keong Lew, Joan Redwing, Theresa Mayer

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

The results of four-point resistivity and gate-dependent conductance measurements taken on unintentionally-doped, p-type and n-type silicon nanowires (SiNWs), are presented. The SiNWs used in the studies are synthesized by template-directed vapor-liquid-solid (VLS) growth using 10% SiH ₄ in H ₂ as silicon gas source. The data show a clear trend to lower resistivity when b- and p-dopants are unintentionally added during VLS growth. The results of the study show that future efforts should address the source of the high p-type background doping concentration in VLS grown SiNWs to facilitate improvements in the properties of n-channel devices.

Original language	English (US)
Title of host publication	Device Research Conference - Conference Digest, 62nd DRC
Pages	23-24
Number of pages	2
DOIs	https://doi.org/10.1109/DRC.2004.1367764
State	Published - 2004
Event	Device Research Conference - Conference Digest, 62nd DRC - Notre Dame, IN, United States Duration: Jun 21 2004 → Jun 23 2004

Publication series

Name	Device Research Conference - Conference Digest, DRC
ISSN (Print)	1548-3770

Other

Other	Device Research Conference - Conference Digest, 62nd DRC
Country/Territory	United States
City	Notre Dame, IN
Period	6/21/04 → 6/23/04

All Science Journal Classification (ASJC) codes

General Engineering

Access to Document

10.1109/DRC.2004.1367764

Cite this

@inproceedings{f44f173c5a454f82b2b2eddcaf808705,

title = "Electrical properties of p- and n-type silicon nanowires",

abstract = "The results of four-point resistivity and gate-dependent conductance measurements taken on unintentionally-doped, p-type and n-type silicon nanowires (SiNWs), are presented. The SiNWs used in the studies are synthesized by template-directed vapor-liquid-solid (VLS) growth using 10% SiH 4 in H 2 as silicon gas source. The data show a clear trend to lower resistivity when b- and p-dopants are unintentionally added during VLS growth. The results of the study show that future efforts should address the source of the high p-type background doping concentration in VLS grown SiNWs to facilitate improvements in the properties of n-channel devices.",

author = "Yanfeng Wang and Marco Cabassi and Ho, {Tsung Ta} and Lew, {Kok Keong} and Joan Redwing and Theresa Mayer",

year = "2004",

doi = "10.1109/DRC.2004.1367764",

language = "English (US)",

isbn = "0780382846",

series = "Device Research Conference - Conference Digest, DRC",

pages = "23--24",

booktitle = "Device Research Conference - Conference Digest, 62nd DRC",

note = "Device Research Conference - Conference Digest, 62nd DRC ; Conference date: 21-06-2004 Through 23-06-2004",

}

Wang, Y, Cabassi, M, Ho, TT, Lew, KK, Redwing, J & Mayer, T 2004, Electrical properties of p- and n-type silicon nanowires. in Device Research Conference - Conference Digest, 62nd DRC., II.A.-6, Device Research Conference - Conference Digest, DRC, pp. 23-24, Device Research Conference - Conference Digest, 62nd DRC, Notre Dame, IN, United States, 6/21/04. https://doi.org/10.1109/DRC.2004.1367764

TY - GEN

T1 - Electrical properties of p- and n-type silicon nanowires

AU - Wang, Yanfeng

AU - Cabassi, Marco

AU - Ho, Tsung Ta

AU - Lew, Kok Keong

AU - Redwing, Joan

AU - Mayer, Theresa

PY - 2004

Y1 - 2004

N2 - The results of four-point resistivity and gate-dependent conductance measurements taken on unintentionally-doped, p-type and n-type silicon nanowires (SiNWs), are presented. The SiNWs used in the studies are synthesized by template-directed vapor-liquid-solid (VLS) growth using 10% SiH 4 in H 2 as silicon gas source. The data show a clear trend to lower resistivity when b- and p-dopants are unintentionally added during VLS growth. The results of the study show that future efforts should address the source of the high p-type background doping concentration in VLS grown SiNWs to facilitate improvements in the properties of n-channel devices.

AB - The results of four-point resistivity and gate-dependent conductance measurements taken on unintentionally-doped, p-type and n-type silicon nanowires (SiNWs), are presented. The SiNWs used in the studies are synthesized by template-directed vapor-liquid-solid (VLS) growth using 10% SiH 4 in H 2 as silicon gas source. The data show a clear trend to lower resistivity when b- and p-dopants are unintentionally added during VLS growth. The results of the study show that future efforts should address the source of the high p-type background doping concentration in VLS grown SiNWs to facilitate improvements in the properties of n-channel devices.

UR - http://www.scopus.com/inward/record.url?scp=18044392734&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=18044392734&partnerID=8YFLogxK

U2 - 10.1109/DRC.2004.1367764

DO - 10.1109/DRC.2004.1367764

M3 - Conference contribution

AN - SCOPUS:18044392734

SN - 0780382846

T3 - Device Research Conference - Conference Digest, DRC

SP - 23

EP - 24

BT - Device Research Conference - Conference Digest, 62nd DRC

T2 - Device Research Conference - Conference Digest, 62nd DRC

Y2 - 21 June 2004 through 23 June 2004

ER -

Electrical properties of p- and n-type silicon nanowires

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this