Elimination of DC voltage sources and reduction of power switches voltage stress in stacked multicell converters: Analysis, modeling, and implementation

SUMMARY Multilevel converters have been widely used in medium-voltage high-power applications. One of the typical breeds of multicell converters is stacked multicell converter (SMC). This paper presents an improved configuration for SMCs, accompanied by its analysis, modeling, and implementation. The main advantages of the proposed converter, in comparison with the conventional one, are that the numbers of required dc voltage sources are halved in the improved topology and also the voltage rating of half of the power switches are decreased by 50% which results in reducing the cost, size, and weight of the SMCs effectively. This progress is achieved by connecting the upper stacks to the lower stacks back to back while the number of high-frequency power switches and flying capacitors (FCs), voltage ratings of FCs, as well as the number of high-frequency switchings during a full cycle are kept constant. The control methodology is based on the phase-shifted carrier sinusoidal pulse width modulation technique; therefore, the well-known natural balancing phenomenon of FC voltages, one of the critical advantages of SMCs, is maintained in the proposed converter. This paper also presents an analytic model to study and analyze the dynamic of FC voltages in the proposed SMC. Numerical analysis results of the derived analytic model, simulation results, and, moreover, measurements taken from the laboratory prototypes are presented in order to validate the effectiveness and advantages of the proposed configuration as well as its control strategy and analytic model. In addition, the comparison of the proposed converter with other types of multilevel converters is carried out to highlight the advantages of the proposed structure.