TY - GEN
T1 - Emerging reconfigurable nanotechnologies
T2 - 37th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018
AU - Rai, Shubham
AU - Srinivasa, Srivatsa
AU - Cadareanu, Patsy
AU - Yin, Xunzhao
AU - Hu, Xiaobo Sharon
AU - Gaillardon, Pierre Emmanuel
AU - Narayanan, Vijaykrishnan
AU - Kumar, Akash
N1 - Funding Information:
This work is supported in part by the German Research Foundation (DFG) within the Cluster of Excellence Center for Advancing Electronics Dresden, the NSF Career Award number 1751064, SRC JUMP Center for Research on Intelligent Storage and Processing-in-memory, and Indiana Innovation Institute through the ASSURE Program.
Publisher Copyright:
© 2018 ACM.
PY - 2018/11/5
Y1 - 2018/11/5
N2 - Several emerging reconfigurable technologies have been explored in recent years offering device level runtime reconfigurability. These technologies offer the freedom to choose between p- and n-type functionality from a single transistor. In order to optimally utilize the feature-sets of these technologies, circuit designs and storage elements require novel design to complement the existing and future electronic requirements. An important aspect to sustain such endeavors is to supplement the existing design flow from the device level to the circuit level. This should be backed by a thorough evaluation so as to ascertain the feasibility of such explorations. Additionally, since these technologies offer runtime reconfigurability and often encapsulate more than one functions, hardware security features like polymorphic logic gates and on-chip key storage come naturally cheap with circuits based on these reconfigurable technologies. This paper presents innovative approaches devised for circuit designs harnessing the reconfigurable features of these nanotechnologies. New circuit design paradigms based on these nano devices will be discussed to brainstorm on exciting avenues for novel computing elements.
AB - Several emerging reconfigurable technologies have been explored in recent years offering device level runtime reconfigurability. These technologies offer the freedom to choose between p- and n-type functionality from a single transistor. In order to optimally utilize the feature-sets of these technologies, circuit designs and storage elements require novel design to complement the existing and future electronic requirements. An important aspect to sustain such endeavors is to supplement the existing design flow from the device level to the circuit level. This should be backed by a thorough evaluation so as to ascertain the feasibility of such explorations. Additionally, since these technologies offer runtime reconfigurability and often encapsulate more than one functions, hardware security features like polymorphic logic gates and on-chip key storage come naturally cheap with circuits based on these reconfigurable technologies. This paper presents innovative approaches devised for circuit designs harnessing the reconfigurable features of these nanotechnologies. New circuit design paradigms based on these nano devices will be discussed to brainstorm on exciting avenues for novel computing elements.
UR - http://www.scopus.com/inward/record.url?scp=85058165888&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85058165888&partnerID=8YFLogxK
U2 - 10.1145/3240765.3243472
DO - 10.1145/3240765.3243472
M3 - Conference contribution
AN - SCOPUS:85058165888
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
BT - 2018 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 5 November 2018 through 8 November 2018
ER -