Enabling 3-D design

Arthur Keigler, Kathy O'Donnell, Liu Zhenqiu, Wu Bill, John Trezza

Research output: Contribution to specialist publicationArticle

5 Scopus citations


Pilot-level fabrication of wafers integrated into 3-D structures have been processed. These demonstrate the repeatability and reliability of the Au/Sn penetration/post-joining process and a fine-pitch TSV process suitable for thin wafer handling. Reliability testing shows that this 3-D architecture exceeds customer requirements. An IC design with stacked memory demonstrated a 1000-fold increase in speed with a 100-fold decrease in power consumption. This shows the groundbreaking capability of using 3-D processing to combine the design capabilities of a fabless company with the processing capabilities of both front-end and packaging foundries to create a high-performance device without resorting to leading-edge transistor geometries.

Original languageEnglish (US)
Number of pages9
Specialist publicationSemiconductor International
StatePublished - Aug 2007

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Microbiology
  • Condensed Matter Physics
  • Electrical and Electronic Engineering


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