TY - JOUR
T1 - Enabling Energy-Efficient Nonvolatile Computing with Negative Capacitance FET
AU - Li, Xueqing
AU - Sampson, John
AU - Khan, Asif
AU - Ma, Kaisheng
AU - George, Sumitha
AU - Aziz, Ahmedullah
AU - Gupta, Sumeet Kumar
AU - Salahuddin, Sayeef
AU - Chang, Meng Fan
AU - Datta, Suman
AU - Narayanan, Vijaykrishnan
N1 - Publisher Copyright:
© 1963-2012 IEEE.
PY - 2017/8
Y1 - 2017/8
N2 - Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the I D - V G hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R DS ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R DS ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3-0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications.
AB - Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the I D - V G hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R DS ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R DS ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3-0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications.
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U2 - 10.1109/TED.2017.2716338
DO - 10.1109/TED.2017.2716338
M3 - Article
AN - SCOPUS:85023765455
SN - 0018-9383
VL - 64
SP - 3452
EP - 3458
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 8
M1 - 7959653
ER -