TY - GEN
T1 - Enabling power-efficient designs with III-V tunnel FETs
AU - Kim, Moon Seok
AU - Liu, Huichu
AU - Swaminathan, Karthik
AU - Li, Xueqing
AU - Datta, Suman
AU - Narayanan, Vijaykrishnan
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/12/5
Y1 - 2014/12/5
N2 - III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, uni-directional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level.
AB - III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, uni-directional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level.
UR - http://www.scopus.com/inward/record.url?scp=84920065689&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84920065689&partnerID=8YFLogxK
U2 - 10.1109/CSICS.2014.6978551
DO - 10.1109/CSICS.2014.6978551
M3 - Conference contribution
AN - SCOPUS:84920065689
T3 - Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
BT - Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 36th IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2014
Y2 - 19 October 2014 through 22 October 2014
ER -