Enabling power-efficient designs with III-V tunnel FETs

Moon Seok Kim; Huichu Liu; Karthik Swaminathan; Xueqing Li; Suman Datta; Vijaykrishnan Narayanan

doi:10.1109/CSICS.2014.6978551

Enabling power-efficient designs with III-V tunnel FETs

Moon Seok Kim, Huichu Liu, Karthik Swaminathan, Xueqing Li, Suman Datta, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Scopus citations

Abstract

III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, uni-directional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level.

Original language	English (US)
Title of host publication	Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479936229
DOIs	https://doi.org/10.1109/CSICS.2014.6978551
State	Published - Dec 5 2014
Event	36th IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2014 - San Diego, United States Duration: Oct 19 2014 → Oct 22 2014

Publication series

Name	Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
ISSN (Print)	1550-8781

Other

Other	36th IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2014
Country/Territory	United States
City	San Diego
Period	10/19/14 → 10/22/14

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Condensed Matter Physics
Electronic, Optical and Magnetic Materials

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10.1109/CSICS.2014.6978551

Cite this

Kim, M. S., Liu, H., Swaminathan, K., Li, X., Datta, S., & Narayanan, V. (2014). Enabling power-efficient designs with III-V tunnel FETs. In Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC Article 6978551 (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CSICS.2014.6978551

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abstract = "III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, uni-directional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level.",

author = "Kim, {Moon Seok} and Huichu Liu and Karthik Swaminathan and Xueqing Li and Suman Datta and Vijaykrishnan Narayanan",

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Kim, MS, Liu, H, Swaminathan, K, Li, X, Datta, S & Narayanan, V 2014, Enabling power-efficient designs with III-V tunnel FETs. in Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC., 6978551, Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC, Institute of Electrical and Electronics Engineers Inc., 36th IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2014, San Diego, United States, 10/19/14. https://doi.org/10.1109/CSICS.2014.6978551

Enabling power-efficient designs with III-V tunnel FETs. / Kim, Moon Seok; Liu, Huichu; Swaminathan, Karthik et al.
Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC. Institute of Electrical and Electronics Engineers Inc., 2014. 6978551 (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Enabling power-efficient designs with III-V tunnel FETs

AU - Kim, Moon Seok

AU - Liu, Huichu

AU - Swaminathan, Karthik

AU - Li, Xueqing

AU - Datta, Suman

AU - Narayanan, Vijaykrishnan

PY - 2014/12/5

Y1 - 2014/12/5

N2 - III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, uni-directional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level.

AB - III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, uni-directional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level.

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DO - 10.1109/CSICS.2014.6978551

M3 - Conference contribution

AN - SCOPUS:84920065689

T3 - Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

BT - Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 36th IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2014

Y2 - 19 October 2014 through 22 October 2014

ER -

Kim MS, Liu H, Swaminathan K, Li X, Datta S, Narayanan V. Enabling power-efficient designs with III-V tunnel FETs. In Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC. Institute of Electrical and Electronics Engineers Inc. 2014. 6978551. (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC). doi: 10.1109/CSICS.2014.6978551

Enabling power-efficient designs with III-V tunnel FETs

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