Energy and timing characterization of VLSI charge-pump phase-locked loops

D. Duarte; Vijaykrishnan Narayanan; Mary Jane Irwin

doi:10.1109/SOC.2003.1241539

Energy and timing characterization of VLSI charge-pump phase-locked loops

D. Duarte
, Vijaykrishnan Narayanan
, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Phased locked loops (PLLs) are frequently employed in high-speed communication links, RF demodulation systems and SOCs for frequency synthesis. As wireless portable systems become standard, performance and power PLL models are essential in order to explore design trade-offs and feasible power reductions. We present a PLL timing model, review results of our power model and couple them with expressions for jitter estimation. The model has been validated and shown to be within 5% of circuit level simulation numbers.

Original language	English (US)
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2003
Editors	Dong S. Ha, Richard Auletta, John Chickanosky
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	341-344
Number of pages	4
ISBN (Electronic)	0780381823, 9780780381827
DOIs	https://doi.org/10.1109/SOC.2003.1241539
State	Published - Jan 1 2003
Event	IEEE International SOC Conference, SOCC 2003 - Portland, United States Duration: Sep 17 2003 → Sep 20 2003

Other

Other	IEEE International SOC Conference, SOCC 2003
Country/Territory	United States
City	Portland
Period	9/17/03 → 9/20/03

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/SOC.2003.1241539

Cite this

@inproceedings{143d45ab91ee4a029500e51d84d29850,

title = "Energy and timing characterization of VLSI charge-pump phase-locked loops",

abstract = "Phased locked loops (PLLs) are frequently employed in high-speed communication links, RF demodulation systems and SOCs for frequency synthesis. As wireless portable systems become standard, performance and power PLL models are essential in order to explore design trade-offs and feasible power reductions. We present a PLL timing model, review results of our power model and couple them with expressions for jitter estimation. The model has been validated and shown to be within 5\% of circuit level simulation numbers.",

author = "D. Duarte and Vijaykrishnan Narayanan and Irwin, \{Mary Jane\}",

year = "2003",

month = jan,

day = "1",

doi = "10.1109/SOC.2003.1241539",

language = "English (US)",

pages = "341--344",

editor = "Ha, \{Dong S.\} and Richard Auletta and John Chickanosky",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE International SOC Conference, SOCC 2003 ; Conference date: 17-09-2003 Through 20-09-2003",

}

Duarte, D, Narayanan, V & Irwin, MJ 2003, Energy and timing characterization of VLSI charge-pump phase-locked loops. in DS Ha, R Auletta & J Chickanosky (eds), Proceedings - IEEE International SOC Conference, SOCC 2003., 1241539, Institute of Electrical and Electronics Engineers Inc., pp. 341-344, IEEE International SOC Conference, SOCC 2003, Portland, United States, 9/17/03. https://doi.org/10.1109/SOC.2003.1241539

Energy and timing characterization of VLSI charge-pump phase-locked loops. / Duarte, D.; Narayanan, Vijaykrishnan; Irwin, Mary Jane.
Proceedings - IEEE International SOC Conference, SOCC 2003. ed. / Dong S. Ha; Richard Auletta; John Chickanosky. Institute of Electrical and Electronics Engineers Inc., 2003. p. 341-344 1241539.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Energy and timing characterization of VLSI charge-pump phase-locked loops

AU - Duarte, D.

AU - Narayanan, Vijaykrishnan

AU - Irwin, Mary Jane

PY - 2003/1/1

Y1 - 2003/1/1

N2 - Phased locked loops (PLLs) are frequently employed in high-speed communication links, RF demodulation systems and SOCs for frequency synthesis. As wireless portable systems become standard, performance and power PLL models are essential in order to explore design trade-offs and feasible power reductions. We present a PLL timing model, review results of our power model and couple them with expressions for jitter estimation. The model has been validated and shown to be within 5% of circuit level simulation numbers.

AB - Phased locked loops (PLLs) are frequently employed in high-speed communication links, RF demodulation systems and SOCs for frequency synthesis. As wireless portable systems become standard, performance and power PLL models are essential in order to explore design trade-offs and feasible power reductions. We present a PLL timing model, review results of our power model and couple them with expressions for jitter estimation. The model has been validated and shown to be within 5% of circuit level simulation numbers.

UR - https://www.scopus.com/pages/publications/84945373605

UR - https://www.scopus.com/pages/publications/84945373605#tab=citedBy

U2 - 10.1109/SOC.2003.1241539

DO - 10.1109/SOC.2003.1241539

M3 - Conference contribution

AN - SCOPUS:84945373605

SP - 341

EP - 344

BT - Proceedings - IEEE International SOC Conference, SOCC 2003

A2 - Ha, Dong S.

A2 - Auletta, Richard

A2 - Chickanosky, John

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International SOC Conference, SOCC 2003

Y2 - 17 September 2003 through 20 September 2003

ER -

Energy and timing characterization of VLSI charge-pump phase-locked loops

Abstract

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