Energy barrier model of SRAM for improved energy and error rates

Jayita Das, Swaroop Ghosh

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


We propose an energy barrier model of Static Random Access Memory (SRAM). The model provides useful insights about memory error rates for write, read, and retention. We introduce the concept of intrinsic energy margin induced write failure. The proposed model is employed for evaluating various write and read assist mechanisms and their potential in modulating the memory failures. Our analysis reveals that this model is very effective in predicting the behavior of SRAM stability and can be used as a tool to expedite the early phases of design to build assist circuits. Additionally, it can also be used to optimize energy dissipation of SRAM cache.

Original languageEnglish (US)
Article number6856229
Pages (from-to)2299-2308
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number8
StatePublished - Aug 2014

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Hardware and Architecture


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