Energy-efficient instruction cache using page-based placement

S. Kim; N. Vijaykrishnan; M. Kandemir; M. J. Irwin

doi:10.1145/502217.502256

Energy-efficient instruction cache using page-based placement

S. Kim
, N. Vijaykrishnan
, M. Kandemir
, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

Energy consumption is a crucial factor in designing battery- operated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments. In order to optimize energy and energy-delay in the memory system, we investigate ways of splitting the instruction cache into several smaller units, each of which is a cache by itself (called subcache). The subcache architecture employs a page-based placement strategy, a dynamic cache line remapping policy and a predictive precharging policy in order to improve the memory system energy behavior. Using applications from the SPECjvm98 and SPECint2000 benchmarks, the proposed subcache architecture is shown to be effective in improving both the energy and energy-delay metrics.

Original language	English (US)
Title of host publication	CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
Publisher	Association for Computing Machinery, Inc
Pages	229-237
Number of pages	9
ISBN (Electronic)	1581133995, 9781581133998
DOIs	https://doi.org/10.1145/502217.502256
State	Published - Nov 16 2001
Event	2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001 - Atlanta, United States Duration: Nov 16 2001 → Nov 17 2001

Publication series

Name	CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Other

Other	2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001
Country/Territory	United States
City	Atlanta
Period	11/16/01 → 11/17/01

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Software
Electrical and Electronic Engineering

Access to Document

10.1145/502217.502256

Cite this

Kim, S., Vijaykrishnan, N., Kandemir, M., & Irwin, M. J. (2001). Energy-efficient instruction cache using page-based placement. In CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (pp. 229-237). (CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems). Association for Computing Machinery, Inc. https://doi.org/10.1145/502217.502256

Kim, S. ; Vijaykrishnan, N. ; Kandemir, M. et al. / Energy-efficient instruction cache using page-based placement. CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. Association for Computing Machinery, Inc, 2001. pp. 229-237 (CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems).

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title = "Energy-efficient instruction cache using page-based placement",

abstract = "Energy consumption is a crucial factor in designing battery- operated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments. In order to optimize energy and energy-delay in the memory system, we investigate ways of splitting the instruction cache into several smaller units, each of which is a cache by itself (called subcache). The subcache architecture employs a page-based placement strategy, a dynamic cache line remapping policy and a predictive precharging policy in order to improve the memory system energy behavior. Using applications from the SPECjvm98 and SPECint2000 benchmarks, the proposed subcache architecture is shown to be effective in improving both the energy and energy-delay metrics.",

author = "S. Kim and N. Vijaykrishnan and M. Kandemir and Irwin, \{M. J.\}",

note = "Funding Information: This work was supported in part by NSF grants 0073419, 0082064, 0093082, 0093085, and GSRC. Publisher Copyright: Copyright 2001 ACM.; 2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001 ; Conference date: 16-11-2001 Through 17-11-2001",

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doi = "10.1145/502217.502256",

language = "English (US)",

series = "CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems",

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}

Kim, S, Vijaykrishnan, N , Kandemir, M & Irwin, MJ 2001, Energy-efficient instruction cache using page-based placement. in CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, Association for Computing Machinery, Inc, pp. 229-237, 2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001, Atlanta, United States, 11/16/01. https://doi.org/10.1145/502217.502256

Energy-efficient instruction cache using page-based placement. / Kim, S.; Vijaykrishnan, N.; Kandemir, M. et al.
CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. Association for Computing Machinery, Inc, 2001. p. 229-237 (CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Energy-efficient instruction cache using page-based placement

AU - Kim, S.

AU - Vijaykrishnan, N.

AU - Kandemir, M.

AU - Irwin, M. J.

PY - 2001/11/16

Y1 - 2001/11/16

N2 - Energy consumption is a crucial factor in designing battery- operated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments. In order to optimize energy and energy-delay in the memory system, we investigate ways of splitting the instruction cache into several smaller units, each of which is a cache by itself (called subcache). The subcache architecture employs a page-based placement strategy, a dynamic cache line remapping policy and a predictive precharging policy in order to improve the memory system energy behavior. Using applications from the SPECjvm98 and SPECint2000 benchmarks, the proposed subcache architecture is shown to be effective in improving both the energy and energy-delay metrics.

AB - Energy consumption is a crucial factor in designing battery- operated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments. In order to optimize energy and energy-delay in the memory system, we investigate ways of splitting the instruction cache into several smaller units, each of which is a cache by itself (called subcache). The subcache architecture employs a page-based placement strategy, a dynamic cache line remapping policy and a predictive precharging policy in order to improve the memory system energy behavior. Using applications from the SPECjvm98 and SPECint2000 benchmarks, the proposed subcache architecture is shown to be effective in improving both the energy and energy-delay metrics.

UR - https://www.scopus.com/pages/publications/85024273712

UR - https://www.scopus.com/pages/publications/85024273712#tab=citedBy

U2 - 10.1145/502217.502256

DO - 10.1145/502217.502256

M3 - Conference contribution

AN - SCOPUS:85024273712

T3 - CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

SP - 229

EP - 237

BT - CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

PB - Association for Computing Machinery, Inc

T2 - 2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001

Y2 - 16 November 2001 through 17 November 2001

ER -

Kim S, Vijaykrishnan N , Kandemir M, Irwin MJ. Energy-efficient instruction cache using page-based placement. In CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. Association for Computing Machinery, Inc. 2001. p. 229-237. (CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems). doi: 10.1145/502217.502256

Energy-efficient instruction cache using page-based placement

Abstract

Publication series

Other

UN SDGs

All Science Journal Classification (ASJC) codes

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