Enhancement mode strained (1.3%) germanium quantum well FinFET (WFin=20nm) with high mobility (μHole=700 cm2/Vs), low EOT (∼0.7nm) on bulk silicon substrate

A. Agrawal; M. Barth; G. B. Rayner; V. T. Arun; C. Eichfeld; G. Lavallee; S. Y. Yu; X. Sang; S. Brookes; Y. Zheng; Y. J. Lee; Y. R. Lin; C. H. Wu; C. H. Ko; J. LeBeau; R. Engel-Herbert; S. E. Mohney; Y. C. Yeo; S. Datta

doi:10.1109/IEDM.2014.7047064

Enhancement mode strained (1.3%) germanium quantum well FinFET (W_Fin=20nm) with high mobility (μ_Hole=700 cm²/Vs), low EOT (∼0.7nm) on bulk silicon substrate

A. Agrawal, M. Barth, G. B. Rayner, V. T. Arun, C. Eichfeld, G. Lavallee, S. Y. Yu, X. Sang, S. Brookes, Y. Zheng, Y. J. Lee, Y. R. Lin, C. H. Wu, C. H. Ko, J. LeBeau, R. Engel-Herbert, S. E. Mohney, Y. C. Yeo, S. Datta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Scopus citations

Abstract

Compressively strained Ge (s-Ge) quantum well (QW) FinFETs with Si_0.3Ge_0.7 buffer are fabricated on 300mm bulk Si substrate with 20nm W_Fin and 80nm fin pitch using sidewall image transfer (SIT) patterning process. We demonstrate (a) in-situ process flow for a tri-layer high-κ dielectric HfO₂/Al₂O₃/GeO_x gate stack achieving ultrathin EOT of 0.7nm with low D_IT and low gate leakage; (b) 1.3% s-Ge FinFETs with Phosphorus doped Si_0.3Ge_0.7 buffer on bulk Si substrate exhibiting peak μ_h=700 cm²/V_s, μ_h=220 cm²/Vs at 10¹³ /cm² hole density. The s-Ge FinFETs achieve the highest μ∗C_max of 3.1×10^-4 F/Vs resulting in 5x higher I_ON over unstrained Ge FinFETs.

Original language	English (US)
Title of host publication	2014 IEEE International Electron Devices Meeting, IEDM 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	16.4.1-16.4.4
Edition	February
ISBN (Electronic)	9781479980017
DOIs	https://doi.org/10.1109/IEDM.2014.7047064
State	Published - Feb 20 2015
Event	2014 60th IEEE International Electron Devices Meeting, IEDM 2014 - San Francisco, United States Duration: Dec 15 2014 → Dec 17 2014

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Number	February
Volume	2015-February
ISSN (Print)	0163-1918

Other

Other	2014 60th IEEE International Electron Devices Meeting, IEDM 2014
Country/Territory	United States
City	San Francisco
Period	12/15/14 → 12/17/14

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM.2014.7047064

Cite this

Agrawal, A., Barth, M., Rayner, G. B., Arun, V. T., Eichfeld, C., Lavallee, G., Yu, S. Y., Sang, X., Brookes, S., Zheng, Y., Lee, Y. J., Lin, Y. R., Wu, C. H., Ko, C. H., LeBeau, J., Engel-Herbert, R., Mohney, S. E., Yeo, Y. C., & Datta, S. (2015). Enhancement mode strained (1.3%) germanium quantum well FinFET (W_Fin=20nm) with high mobility (μ_Hole=700 cm²/Vs), low EOT (∼0.7nm) on bulk silicon substrate. In 2014 IEEE International Electron Devices Meeting, IEDM 2014 (February ed., pp. 16.4.1-16.4.4). Article 7047064 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2015-February, No. February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2014.7047064

Agrawal, A. ; Barth, M. ; Rayner, G. B. et al. / Enhancement mode strained (1.3%) germanium quantum well FinFET (W_Fin=20nm) with high mobility (μ_Hole=700 cm²/Vs), low EOT (∼0.7nm) on bulk silicon substrate. 2014 IEEE International Electron Devices Meeting, IEDM 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 16.4.1-16.4.4 (Technical Digest - International Electron Devices Meeting, IEDM; February).

@inproceedings{8287c88b5bca4867a9ab14a7f2d56721,

title = "Enhancement mode strained (1.3%) germanium quantum well FinFET (WFin=20nm) with high mobility (μHole=700 cm2/Vs), low EOT (∼0.7nm) on bulk silicon substrate",

abstract = "Compressively strained Ge (s-Ge) quantum well (QW) FinFETs with Si0.3Ge0.7 buffer are fabricated on 300mm bulk Si substrate with 20nm WFin and 80nm fin pitch using sidewall image transfer (SIT) patterning process. We demonstrate (a) in-situ process flow for a tri-layer high-κ dielectric HfO2/Al2O3/GeOx gate stack achieving ultrathin EOT of 0.7nm with low DIT and low gate leakage; (b) 1.3% s-Ge FinFETs with Phosphorus doped Si0.3Ge0.7 buffer on bulk Si substrate exhibiting peak μh=700 cm2/Vs, μh=220 cm2/Vs at 1013 /cm2 hole density. The s-Ge FinFETs achieve the highest μ∗Cmax of 3.1×10-4 F/Vs resulting in 5x higher ION over unstrained Ge FinFETs.",

author = "A. Agrawal and M. Barth and Rayner, {G. B.} and Arun, {V. T.} and C. Eichfeld and G. Lavallee and Yu, {S. Y.} and X. Sang and S. Brookes and Y. Zheng and Lee, {Y. J.} and Lin, {Y. R.} and Wu, {C. H.} and Ko, {C. H.} and J. LeBeau and R. Engel-Herbert and Mohney, {S. E.} and Yeo, {Y. C.} and S. Datta",

year = "2015",

month = feb,

day = "20",

doi = "10.1109/IEDM.2014.7047064",

language = "English (US)",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "February",

pages = "16.4.1--16.4.4",

booktitle = "2014 IEEE International Electron Devices Meeting, IEDM 2014",

address = "United States",

edition = "February",

note = "2014 60th IEEE International Electron Devices Meeting, IEDM 2014 ; Conference date: 15-12-2014 Through 17-12-2014",

}

Agrawal, A, Barth, M, Rayner, GB, Arun, VT, Eichfeld, C , Lavallee, G, Yu, SY, Sang, X, Brookes, S, Zheng, Y, Lee, YJ, Lin, YR, Wu, CH, Ko, CH, LeBeau, J, Engel-Herbert, R, Mohney, SE, Yeo, YC & Datta, S 2015, Enhancement mode strained (1.3%) germanium quantum well FinFET (W_Fin=20nm) with high mobility (μ_Hole=700 cm²/Vs), low EOT (∼0.7nm) on bulk silicon substrate. in 2014 IEEE International Electron Devices Meeting, IEDM 2014. February edn, 7047064, Technical Digest - International Electron Devices Meeting, IEDM, no. February, vol. 2015-February, Institute of Electrical and Electronics Engineers Inc., pp. 16.4.1-16.4.4, 2014 60th IEEE International Electron Devices Meeting, IEDM 2014, San Francisco, United States, 12/15/14. https://doi.org/10.1109/IEDM.2014.7047064

Enhancement mode strained (1.3%) germanium quantum well FinFET (W_Fin=20nm) with high mobility (μ_Hole=700 cm²/Vs), low EOT (∼0.7nm) on bulk silicon substrate. / Agrawal, A.; Barth, M.; Rayner, G. B. et al.
2014 IEEE International Electron Devices Meeting, IEDM 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. p. 16.4.1-16.4.4 7047064 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2015-February, No. February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Enhancement mode strained (1.3%) germanium quantum well FinFET (WFin=20nm) with high mobility (μHole=700 cm2/Vs), low EOT (∼0.7nm) on bulk silicon substrate

AU - Agrawal, A.

AU - Barth, M.

AU - Rayner, G. B.

AU - Arun, V. T.

AU - Eichfeld, C.

AU - Lavallee, G.

AU - Yu, S. Y.

AU - Sang, X.

AU - Brookes, S.

AU - Zheng, Y.

AU - Lee, Y. J.

AU - Lin, Y. R.

AU - Wu, C. H.

AU - Ko, C. H.

AU - LeBeau, J.

AU - Engel-Herbert, R.

AU - Mohney, S. E.

AU - Yeo, Y. C.

AU - Datta, S.

PY - 2015/2/20

Y1 - 2015/2/20

N2 - Compressively strained Ge (s-Ge) quantum well (QW) FinFETs with Si0.3Ge0.7 buffer are fabricated on 300mm bulk Si substrate with 20nm WFin and 80nm fin pitch using sidewall image transfer (SIT) patterning process. We demonstrate (a) in-situ process flow for a tri-layer high-κ dielectric HfO2/Al2O3/GeOx gate stack achieving ultrathin EOT of 0.7nm with low DIT and low gate leakage; (b) 1.3% s-Ge FinFETs with Phosphorus doped Si0.3Ge0.7 buffer on bulk Si substrate exhibiting peak μh=700 cm2/Vs, μh=220 cm2/Vs at 1013 /cm2 hole density. The s-Ge FinFETs achieve the highest μ∗Cmax of 3.1×10-4 F/Vs resulting in 5x higher ION over unstrained Ge FinFETs.

AB - Compressively strained Ge (s-Ge) quantum well (QW) FinFETs with Si0.3Ge0.7 buffer are fabricated on 300mm bulk Si substrate with 20nm WFin and 80nm fin pitch using sidewall image transfer (SIT) patterning process. We demonstrate (a) in-situ process flow for a tri-layer high-κ dielectric HfO2/Al2O3/GeOx gate stack achieving ultrathin EOT of 0.7nm with low DIT and low gate leakage; (b) 1.3% s-Ge FinFETs with Phosphorus doped Si0.3Ge0.7 buffer on bulk Si substrate exhibiting peak μh=700 cm2/Vs, μh=220 cm2/Vs at 1013 /cm2 hole density. The s-Ge FinFETs achieve the highest μ∗Cmax of 3.1×10-4 F/Vs resulting in 5x higher ION over unstrained Ge FinFETs.

UR - http://www.scopus.com/inward/record.url?scp=84938259941&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84938259941&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2014.7047064

DO - 10.1109/IEDM.2014.7047064

M3 - Conference contribution

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 16.4.1-16.4.4

BT - 2014 IEEE International Electron Devices Meeting, IEDM 2014

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2014 60th IEEE International Electron Devices Meeting, IEDM 2014

Y2 - 15 December 2014 through 17 December 2014

ER -

Agrawal A, Barth M, Rayner GB, Arun VT, Eichfeld C , Lavallee G et al. Enhancement mode strained (1.3%) germanium quantum well FinFET (W_Fin=20nm) with high mobility (μ_Hole=700 cm²/Vs), low EOT (∼0.7nm) on bulk silicon substrate. In 2014 IEEE International Electron Devices Meeting, IEDM 2014. February ed. Institute of Electrical and Electronics Engineers Inc. 2015. p. 16.4.1-16.4.4. 7047064. (Technical Digest - International Electron Devices Meeting, IEDM; February). doi: 10.1109/IEDM.2014.7047064