Erase-Verify Operation in Ferroelectric 3D Vertical NAND Storage

Ferroelectric 3D vertical NAND offers attractive benefits such as lower stack height and reduced write voltage, but enabling erase-verify remains a significant challenge because the erase operation places all FeFETs into a high-threshold-voltage (HVT) state, suppressing electron conduction through the string. This makes conventional electron-based erase-verify schemes ineffective. In this work, we propose a GIDL-assisted hole-based erase-verify method that generates holes through band-to-band tunneling in the source-side transistor and uses their propagation to distinguish fully erased (all-HVT) strings from those containing fail-to-erase low-Vth (LVT) cells. TCAD simulations show that GIDL-generated holes can propagate across an all-HVT string, raising the bitline potential, while an LVT FeFET blocks hole transport, enabling robust verify sensing. We further analyze device-level reliability considerations and evaluate the impact of channel thickness on sense margin. The proposed GIDL-assisted approach provides a compact and architecture-compatible solution for erase-verify in FE-NAND without modifying channel type, adding p+ regions, or requiring incremental erase schemes.