TY - GEN
T1 - Evaluating run-time techniques for leakage power reduction
AU - Duarte, D.
AU - Tsai, Yuh Fang
AU - Vijaykrishnan, N.
AU - Irwin, M. J.
N1 - Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter kind and compare three techniques: input vector control, body bias control and power supply gating. We determine their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead. The importance of the 'minimum idle time' parameter, as an additional evaluation tool, is emphasized, as well as the feasibility of achieving power supply gating at low levels of granularity. The obtained data supports the formulation of a comprehensive leakage reduction scheme, in which each technique is targeted for certain types of functional units and a given level of granularity depending on the incurred overhead cost and the obtainable savings.
AB - While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter kind and compare three techniques: input vector control, body bias control and power supply gating. We determine their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead. The importance of the 'minimum idle time' parameter, as an additional evaluation tool, is emphasized, as well as the feasibility of achieving power supply gating at low levels of granularity. The obtained data supports the formulation of a comprehensive leakage reduction scheme, in which each technique is targeted for certain types of functional units and a given level of granularity depending on the incurred overhead cost and the obtainable savings.
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U2 - 10.1109/ASPDAC.2002.994881
DO - 10.1109/ASPDAC.2002.994881
M3 - Conference contribution
AN - SCOPUS:84962299846
T3 - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
SP - 31
EP - 38
BT - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Y2 - 7 January 2002 through 11 January 2002
ER -