Evaluating the impact of architectural-level optimizations on clock power

Keyphrases

• Architectural Level 100%
• Level Optimization 100%
• Clock Power 100%
• Relative Impact 50%
• Energy Model 50%
• System Energy 50%
• Processor Core 50%
• Cycle-accurate 50%
• Energy Simulator 50%
• Compiler Optimization 50%
• Design Case 50%
• Software Layer 50%
• Cache Architecture 50%
• Clock Gating 50%
• Embedded Architecture 50%
• Power-oriented 50%
• Chip-based 50%
• Overall System 50%

Computer Science

• Architectural Level 100%
• Relative Impact 50%
• Processor Core 50%
• Compiler Optimization 50%
• System on a Chip 50%