Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETs

The electrostrictive 2-D field-effect transistor (EFET) is a steep-slope device that promises to offer aggressive length and voltage scalability. Two key features of this device are its high-drive strength with high ON-OFF current ratio and the isolated back-gate terminal, which provides us the fourth knob to control the transistor drive strength. The disadvantage of the technology is the increased device capacitance incurred due to the additional piezoelectric layer in the transistor structure. Second, although the back-gate biasing of EFETs provides us the fourth knob of control, statically biasing the back gate increases the static power consumption. Despite the idiosyncrasies of the technology, this work shows the use of EFETs in field-programmable gate arrays (FPGAs) to be advantageous because the added energy cost of device capacitance gets amortized by the improvement in performance and energy efficiency of using high-drive EFET transistors in the FPGA interconnect architecture. We also show that co-optimization of back-bias voltage along with transduction efficiency is essential in the FPGA subcircuit level for achieving an energy-efficient architecture. This work highlights the specific design approach tradeoffs that differ from prior CMOS approaches and provides guidance for the engineering parameters necessary for EFETs to evolve as a competitive technology.