TY - GEN
T1 - Experimental evaluation of energy behavior of iteration space tiling
AU - Kandemir, Mahmut
AU - Vijaykrishnan, Narayanan
AU - Irwin, Mary Jane
AU - Kim, Hyun Suk
N1 - Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 2001.
PY - 2001
Y1 - 2001
N2 - Optimizing compilers have traditionally focused on enhancing the performance of a given piece of code.With the proliferation of embedded software, it is becoming important to identify the energy impact of these traditional performance-oriented optimizations and to develop new energy-aware schemes. Towards this goal, this paper explores the energy consumption behavior of one of the widely-used loop-level compiler optimizations, iteration space tiling, by varying a set of software and hardware parameters. Our results show that the choice of tile size and input size critically impacts the system energy consumption. Specifically, we find that the best tile size for the least energy consumed is different from that for the best performance. Also, tailoring tile size to the input size generates better energy results than working with a fixed tile size. Our results also reveal that tiling should be applied more or less aggressively based on whether the low power objective is to prolong the battery life or to limit the energy dissipated within a package.
AB - Optimizing compilers have traditionally focused on enhancing the performance of a given piece of code.With the proliferation of embedded software, it is becoming important to identify the energy impact of these traditional performance-oriented optimizations and to develop new energy-aware schemes. Towards this goal, this paper explores the energy consumption behavior of one of the widely-used loop-level compiler optimizations, iteration space tiling, by varying a set of software and hardware parameters. Our results show that the choice of tile size and input size critically impacts the system energy consumption. Specifically, we find that the best tile size for the least energy consumed is different from that for the best performance. Also, tailoring tile size to the input size generates better energy results than working with a fixed tile size. Our results also reveal that tiling should be applied more or less aggressively based on whether the low power objective is to prolong the battery life or to limit the energy dissipated within a package.
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U2 - 10.1007/3-540-45574-4_10
DO - 10.1007/3-540-45574-4_10
M3 - Conference contribution
AN - SCOPUS:84958772665
SN - 3540428623
SN - 9783540455745
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 142
EP - 157
BT - Languages and Compilers for Parallel Computing - 13th International Workshop, LCPC 2000, Revised Papers
A2 - Ferrante, Jeanne
A2 - Midkiff, Samuel P.
A2 - Moreira, Jose E.
A2 - Gupta, Manish
A2 - Chatterjee, Siddhartha
A2 - Prins, Jan
A2 - Pugh, William
A2 - Tseng, Chau-Wen
PB - Springer Verlag
T2 - 13th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2000
Y2 - 10 August 2000 through 12 August 2000
ER -