Experiments with a performance driven module generator

This paper describes a performance-driven module generator for efficient generation of fast static combinational CMOS circuit modules. A new flexible CMOS layout style provides the foundation for implementing fast circuits. Timing optimization is performed via transistor sizing, transistor reordering and the reduction of wiring capacitance on critical paths, all of which are performed in close interaction with the simulated-annealing layout process. The main contributions of this paper are the new layout style that is well-suited for the synthesis of high-speed circuits and the way in which well-known performance optimization techniques are embedded into the layout generation process so as to achieve fine-grain optimization.