TY - GEN
T1 - Exploiting barriers to optimize power consumption of CMPs
AU - Liu, Chun
AU - Sivasubramaniam, Anand
AU - Kandemir, Mahmut
AU - Irwin, Mary Jane
N1 - Copyright:
Copyright 2012 Elsevier B.V., All rights reserved.
PY - 2005
Y1 - 2005
N2 - Power consumption is an important concern for future billion transistor designs. This paper proposes a novel technique for optimizing the power consumption of chip-multiprocessors (CMPs) using an integrated hardware-software mechanism. By using a high level synchronization construct, called the barrier, our technique tracks the idle times spent by a processor waiting for other processors to get to the same point in the program. Using this knowledge, the frequency of the processors can be modulated to reduce/eliminate these idle times, thus providing power savings without compromising on performance. Using real applications from the SpecOMP suite, and a complete system CMP simulator, we demonstrate that this approach can provide as much as 40% power savings (and 32% on the average across five applications) with little impact on performance.
AB - Power consumption is an important concern for future billion transistor designs. This paper proposes a novel technique for optimizing the power consumption of chip-multiprocessors (CMPs) using an integrated hardware-software mechanism. By using a high level synchronization construct, called the barrier, our technique tracks the idle times spent by a processor waiting for other processors to get to the same point in the program. Using this knowledge, the frequency of the processors can be modulated to reduce/eliminate these idle times, thus providing power savings without compromising on performance. Using real applications from the SpecOMP suite, and a complete system CMP simulator, we demonstrate that this approach can provide as much as 40% power savings (and 32% on the average across five applications) with little impact on performance.
UR - http://www.scopus.com/inward/record.url?scp=33746317769&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33746317769&partnerID=8YFLogxK
U2 - 10.1109/IPDPS.2005.211
DO - 10.1109/IPDPS.2005.211
M3 - Conference contribution
AN - SCOPUS:33746317769
SN - 0769523129
SN - 0769523129
SN - 9780769523125
T3 - Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
SP - 5a
BT - Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
T2 - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Y2 - 4 April 2005 through 8 April 2005
ER -