TY - JOUR
T1 - Exploiting heterogeneity for energy efficiency in chip multiprocessors
AU - Saripalli, Vinay
AU - Sun, Guangyu
AU - Mishra, Asit
AU - Xie, Yuan
AU - Datta, Suman
AU - Narayanan, Vijaykrishnan
N1 - Funding Information:
Manuscript received January 15, 2011; accepted May 01, 2011. Date of publication July 25, 2011; date of current version August 19, 2011. This work is supported in part by the Semiconductor Research Corporation Nanoelectronics Research Initiative, the National Institute of Standards and Technology through the Midwest Institute for Nanoelectronics Discovery (MIND), and by NSF Grant 0829926, Grant 0903432, Grant 0916887 and Grant 1028807. This paper was recommended by Guest Editor K. Roy.
PY - 2011/6
Y1 - 2011/6
N2 - Heterogeneous multicores are envisioned to be a promising design paradigm to combat today's challenges of power, memory, and reliability walls that are impeding chip design using deep submicron technology. Future multicores are expected to integrate multiple different cores, including GPGPUs, custom accelerators and configurable cores. In this paper, we introduce an important dimension - technology - using which heterogeneity can be introduced in multicores to improve their energy-performance envelope. Specifically, we analyze the benefits of heterogenous technologies for processor cores and cache subsystems. We discuss two promising device candidates (Tunnel-FET and Magnetic-RAM) for introducing technological diversity in the multicores and analyze their integration in the processor and cache hierarchy in detail. Our analysis shows that introducing such a kind of heterogeneity can significantly enhance the performance and energy behavior of future multicore systems.
AB - Heterogeneous multicores are envisioned to be a promising design paradigm to combat today's challenges of power, memory, and reliability walls that are impeding chip design using deep submicron technology. Future multicores are expected to integrate multiple different cores, including GPGPUs, custom accelerators and configurable cores. In this paper, we introduce an important dimension - technology - using which heterogeneity can be introduced in multicores to improve their energy-performance envelope. Specifically, we analyze the benefits of heterogenous technologies for processor cores and cache subsystems. We discuss two promising device candidates (Tunnel-FET and Magnetic-RAM) for introducing technological diversity in the multicores and analyze their integration in the processor and cache hierarchy in detail. Our analysis shows that introducing such a kind of heterogeneity can significantly enhance the performance and energy behavior of future multicore systems.
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U2 - 10.1109/JETCAS.2011.2158343
DO - 10.1109/JETCAS.2011.2158343
M3 - Article
AN - SCOPUS:80052066953
SN - 2156-3357
VL - 1
SP - 109
EP - 119
JO - IEEE Journal on Emerging and Selected Topics in Circuits and Systems
JF - IEEE Journal on Emerging and Selected Topics in Circuits and Systems
IS - 2
M1 - 5961655
ER -
