TY - GEN
T1 - Exploiting large on-chip memory space through data recomputation
AU - Koc, Hakduran
AU - Kandemir, Mahmut
AU - Ercanli, Ehat
PY - 2010
Y1 - 2010
N2 - This paper presents a novel on-chip memory space utilization strategy for architectures that accommodate large on-chip software-managed memories. In such architectures, the access latencies of data blocks are typically proportional to the distance between the processor and the requested data. Considering such an on-chip memory hierarchy, we propose to recompute the value of an on-chip data, which is far from the processor, using the closer data elements instead of directly accessing the far data if it is beneficial to do so in terms of performance. This paper presents the details of a compiler algorithm that implements the proposed approach and reports the experimental data collected using six data-intensive applications programs. Our experimental evaluation indicates 8.2% performance improvement, on the average, over a state-of-the-art on-chip memory management strategy and shows consistent improvements for varying on-chip memory sizes and different data access latencies.
AB - This paper presents a novel on-chip memory space utilization strategy for architectures that accommodate large on-chip software-managed memories. In such architectures, the access latencies of data blocks are typically proportional to the distance between the processor and the requested data. Considering such an on-chip memory hierarchy, we propose to recompute the value of an on-chip data, which is far from the processor, using the closer data elements instead of directly accessing the far data if it is beneficial to do so in terms of performance. This paper presents the details of a compiler algorithm that implements the proposed approach and reports the experimental data collected using six data-intensive applications programs. Our experimental evaluation indicates 8.2% performance improvement, on the average, over a state-of-the-art on-chip memory management strategy and shows consistent improvements for varying on-chip memory sizes and different data access latencies.
UR - http://www.scopus.com/inward/record.url?scp=79960740898&partnerID=8YFLogxK
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U2 - 10.1109/SOCC.2010.5784683
DO - 10.1109/SOCC.2010.5784683
M3 - Conference contribution
AN - SCOPUS:79960740898
SN - 9781424466832
T3 - Proceedings - IEEE International SOC Conference, SOCC 2010
SP - 513
EP - 518
BT - Proceedings - IEEE International SOC Conference, SOCC 2010
T2 - 23rd IEEE International SOC Conference, SOCC 2010
Y2 - 27 September 2010 through 29 September 2010
ER -