TY - GEN
T1 - Exploiting software pipelining for network-on-chip architectures
AU - Li, Feihui
AU - Kandemir, Mahmut
AU - Kolcu, Ibrahim
PY - 2006
Y1 - 2006
N2 - Recent developments in process technology have made it possible to produce chips consisting of a large number of processing elements. For factors such as scalability, performance, power-efficiency, the interconnection structure supporting such a chip needs to be an on-chip network architecture rather than a conventional bus-based system. Recent research has studied such network-on-chip (NoC) based systems from the performance and throughput, power/energy, reliability, predictability, synchronization, and concurrency perspectives. However, most of these studies are hardware based and it is not clear what type of compiler support would be best suited for these NoC based systems. Focusing on a mesh based NoC architecture that connects multiple processor cores, this paper explores the effectiveness of voltage/frequency scaling for processors and communication links with and without software pipelining, a compiler optimization for increasing parallelism. To our knowledge, this is the first paper that explores the influence of software pipelining in the context of the embedded NoC architectures.
AB - Recent developments in process technology have made it possible to produce chips consisting of a large number of processing elements. For factors such as scalability, performance, power-efficiency, the interconnection structure supporting such a chip needs to be an on-chip network architecture rather than a conventional bus-based system. Recent research has studied such network-on-chip (NoC) based systems from the performance and throughput, power/energy, reliability, predictability, synchronization, and concurrency perspectives. However, most of these studies are hardware based and it is not clear what type of compiler support would be best suited for these NoC based systems. Focusing on a mesh based NoC architecture that connects multiple processor cores, this paper explores the effectiveness of voltage/frequency scaling for processors and communication links with and without software pipelining, a compiler optimization for increasing parallelism. To our knowledge, this is the first paper that explores the influence of software pipelining in the context of the embedded NoC architectures.
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U2 - 10.1109/ISVLSI.2006.43
DO - 10.1109/ISVLSI.2006.43
M3 - Conference contribution
AN - SCOPUS:33749348596
SN - 0769525334
SN - 9780769525334
T3 - Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
SP - 295
EP - 300
BT - Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
T2 - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Y2 - 2 March 2006 through 3 March 2006
ER -