Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

W. Zhang; N. Vijaykrishnan; M. Kandemir; M. J. Irwin; D. Duarte; Y. E. Tsai

doi:10.1109/MICRO.2001.991109

Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

W. Zhang
, N. Vijaykrishnan
, M. Kandemir
, M. J. Irwin
, D. Duarte
, Y. E. Tsai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

50 Scopus citations

Abstract

The mobile computing device market is projected to grow to 16.8 million units in 2004, representing an average annual growth rate of 28% over the five year forecast period [5]. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule slacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit level simulation. Our results show that a unified scheme that uses both dynamic and leakage energy reduction techniques is effective in reducing energy consumption.

Original language	English (US)
Title of host publication	Proceedings of the Annual International Symposium on Microarchitecture
Pages	102-113
Number of pages	12
DOIs	https://doi.org/10.1109/MICRO.2001.991109
State	Published - 2001
Event	34th Annual International Symposium on Microarchitecture ACM/IEEE 2001 - Austin, TX, United States Duration: Dec 1 2001 → Dec 5 2001

Publication series

Name	Proceedings of the Annual International Symposium on Microarchitecture
ISSN (Print)	1072-4451

Other

Other	34th Annual International Symposium on Microarchitecture ACM/IEEE 2001
Country/Territory	United States
City	Austin, TX
Period	12/1/01 → 12/5/01

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Software

Access to Document

10.1109/MICRO.2001.991109

Cite this

Zhang, W., Vijaykrishnan, N., Kandemir, M., Irwin, M. J., Duarte, D., & Tsai, Y. E. (2001). Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. In Proceedings of the Annual International Symposium on Microarchitecture (pp. 102-113). (Proceedings of the Annual International Symposium on Microarchitecture). https://doi.org/10.1109/MICRO.2001.991109

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title = "Exploiting VLIW schedule slacks for dynamic and leakage energy reduction",

abstract = "The mobile computing device market is projected to grow to 16.8 million units in 2004, representing an average annual growth rate of 28\% over the five year forecast period [5]. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule slacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit level simulation. Our results show that a unified scheme that uses both dynamic and leakage energy reduction techniques is effective in reducing energy consumption.",

author = "W. Zhang and N. Vijaykrishnan and M. Kandemir and Irwin, \{M. J.\} and D. Duarte and Tsai, \{Y. E.\}",

year = "2001",

doi = "10.1109/MICRO.2001.991109",

language = "English (US)",

isbn = "0796513697",

series = "Proceedings of the Annual International Symposium on Microarchitecture",

pages = "102--113",

booktitle = "Proceedings of the Annual International Symposium on Microarchitecture",

note = "34th Annual International Symposium on Microarchitecture ACM/IEEE 2001 ; Conference date: 01-12-2001 Through 05-12-2001",

}

Zhang, W, Vijaykrishnan, N , Kandemir, M, Irwin, MJ, Duarte, D & Tsai, YE 2001, Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. in Proceedings of the Annual International Symposium on Microarchitecture. Proceedings of the Annual International Symposium on Microarchitecture, pp. 102-113, 34th Annual International Symposium on Microarchitecture ACM/IEEE 2001, Austin, TX, United States, 12/1/01. https://doi.org/10.1109/MICRO.2001.991109

Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. / Zhang, W.; Vijaykrishnan, N.; Kandemir, M. et al.
Proceedings of the Annual International Symposium on Microarchitecture. 2001. p. 102-113 (Proceedings of the Annual International Symposium on Microarchitecture).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

AU - Zhang, W.

AU - Vijaykrishnan, N.

AU - Kandemir, M.

AU - Irwin, M. J.

AU - Duarte, D.

AU - Tsai, Y. E.

PY - 2001

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AB - The mobile computing device market is projected to grow to 16.8 million units in 2004, representing an average annual growth rate of 28% over the five year forecast period [5]. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule slacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit level simulation. Our results show that a unified scheme that uses both dynamic and leakage energy reduction techniques is effective in reducing energy consumption.

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BT - Proceedings of the Annual International Symposium on Microarchitecture

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ER -

Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

Abstract

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Other

UN SDGs

All Science Journal Classification (ASJC) codes

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