Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications

H. Liu; D. K. Mohata; A. Nidhi; V. Saripalli; V. Narayanan; S. Datta

doi:10.1109/DRC.2012.6256990

Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications

H. Liu
, D. K. Mohata
, A. Nidhi
, V. Saripalli
, V. Narayanan
, S. Datta

Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

24 Scopus citations

Abstract

A vertical device architecture having ∼40% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with L _g=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for V _DD<60;0.6V, while MOSFET is superior for V _DD>0.6V. To further improve MOSFET performance, I _ON needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (C _ov and C _g,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.

Original language	English (US)
Title of host publication	70th Device Research Conference, DRC 2012 - Conference Digest
Pages	233-234
Number of pages	2
DOIs	https://doi.org/10.1109/DRC.2012.6256990
State	Published - 2012
Event	70th Device Research Conference, DRC 2012 - University Park, PA, United States Duration: Jun 18 2012 → Jun 20 2012

Publication series

Name	Device Research Conference - Conference Digest, DRC
ISSN (Print)	1548-3770

Other

Other	70th Device Research Conference, DRC 2012
Country/Territory	United States
City	University Park, PA
Period	6/18/12 → 6/20/12

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/DRC.2012.6256990

Cite this

Liu, H., Mohata, D. K., Nidhi, A., Saripalli, V., Narayanan, V., & Datta, S. (2012). Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications. In 70th Device Research Conference, DRC 2012 - Conference Digest (pp. 233-234). Article 6256990 (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2012.6256990

@inproceedings{f65ed40b9c6f4d8e97b54b779506d345,

title = "Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications",

abstract = "A vertical device architecture having ∼40\% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with L g=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for V DD<60;0.6V, while MOSFET is superior for V DD>0.6V. To further improve MOSFET performance, I ON needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (C ov and C g,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.",

author = "H. Liu and Mohata, \{D. K.\} and A. Nidhi and V. Saripalli and V. Narayanan and S. Datta",

year = "2012",

doi = "10.1109/DRC.2012.6256990",

language = "English (US)",

isbn = "9781467311618",

series = "Device Research Conference - Conference Digest, DRC",

pages = "233--234",

booktitle = "70th Device Research Conference, DRC 2012 - Conference Digest",

note = "70th Device Research Conference, DRC 2012 ; Conference date: 18-06-2012 Through 20-06-2012",

}

Liu, H, Mohata, DK, Nidhi, A, Saripalli, V, Narayanan, V & Datta, S 2012, Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications. in 70th Device Research Conference, DRC 2012 - Conference Digest., 6256990, Device Research Conference - Conference Digest, DRC, pp. 233-234, 70th Device Research Conference, DRC 2012, University Park, PA, United States, 6/18/12. https://doi.org/10.1109/DRC.2012.6256990

Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications. / Liu, H.; Mohata, D. K.; Nidhi, A. et al.
70th Device Research Conference, DRC 2012 - Conference Digest. 2012. p. 233-234 6256990 (Device Research Conference - Conference Digest, DRC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications

AU - Liu, H.

AU - Mohata, D. K.

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AU - Narayanan, V.

AU - Datta, S.

PY - 2012

Y1 - 2012

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AB - A vertical device architecture having ∼40% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with L g=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for V DD<60;0.6V, while MOSFET is superior for V DD>0.6V. To further improve MOSFET performance, I ON needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (C ov and C g,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.

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SN - 9781467311618

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BT - 70th Device Research Conference, DRC 2012 - Conference Digest

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Y2 - 18 June 2012 through 20 June 2012

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Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications

Abstract

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UN SDGs

All Science Journal Classification (ASJC) codes

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