TY - GEN
T1 - Exploring architectural heterogeneity in intelligent vision systems
AU - Chandramoorthy, Nanchini
AU - Tagliavini, Giuseppe
AU - Irick, Kevin
AU - Pullini, Antonio
AU - Advani, Siddharth
AU - Habsi, Sulaiman Al
AU - Cotter, Matthew
AU - Sampson, John
AU - Narayanan, Vijaykrishnan
AU - Benini, Luca
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/3/6
Y1 - 2015/3/6
N2 - Limited power budgets and the need for high performance computing have led to platform customization with a number of accelerators integrated with CMPs. In order to study customized architectures, we model four customization design points and compare their performance and energy across a number of computer vision workloads. We analyze the limitations of generic architectures and quantify the costs of increasing customization using these micro-architectural design points. This analysis leads us to develop a framework consisting of low-power multi-cores and an array of configurable micro-accelerator functional units. Using this platform, we illustrate dataflow and control processing optimizations that provide for performance gains similar to custom ASICs for a wide range of vision benchmarks.
AB - Limited power budgets and the need for high performance computing have led to platform customization with a number of accelerators integrated with CMPs. In order to study customized architectures, we model four customization design points and compare their performance and energy across a number of computer vision workloads. We analyze the limitations of generic architectures and quantify the costs of increasing customization using these micro-architectural design points. This analysis leads us to develop a framework consisting of low-power multi-cores and an array of configurable micro-accelerator functional units. Using this platform, we illustrate dataflow and control processing optimizations that provide for performance gains similar to custom ASICs for a wide range of vision benchmarks.
UR - https://www.scopus.com/pages/publications/84934280193
UR - https://www.scopus.com/inward/citedby.url?scp=84934280193&partnerID=8YFLogxK
U2 - 10.1109/HPCA.2015.7056017
DO - 10.1109/HPCA.2015.7056017
M3 - Conference contribution
AN - SCOPUS:84934280193
T3 - 2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015
SP - 1
EP - 12
BT - 2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015
Y2 - 7 February 2015 through 11 February 2015
ER -