Exploring fault-tolerant network-on-chip architectures

Keyphrases

• Soft Error 100%
• On-chip Interconnects 100%
• Area Overhead 50%
• Reliability Issues 50%
• Architecting 50%
• Valuable Resources 50%
• Network on chip 50%
• Network-on-chip Design 50%
• Energy Overhead 50%
• Transient Failure 50%
• Single Event Upset 50%
• Protection Measures 50%
• Cycle-accurate Simulator 50%
• Deep Submicron Technology 50%

Computer Science

• Fault Tolerant 100%
• Networks on Chips 100%
• Chip Architecture 100%
• Soft Error 66%
• Countermeasures 33%
• Cycle-Accurate Simulator 33%