TY - GEN
T1 - Exploring Simplified Reservoir Computing Systems for Resource-Constrained Edge AI Hardware
AU - Niu, Ziyi
AU - Song, Shuai
AU - Najem, Joseph S.
AU - Syed, Azeemuddin
AU - Hasan, Md Sakib
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - We present a low-overhead reservoir computing framework optimized for edge AI applications by leveraging a combination of several techniques. Specifically, we employ the Simple Cycle Reservoir (SCR) as an alternative to the widely used Echo State Network (ESN), offering a more hardware-efficient design. Our framework evaluates five simplified nonlinear activation functions alongside the conventional hyperbolic tangent function. Additionally, we employ a hyperparameter that enables a tunable trade-off between memory retention and nonlinearity by adjusting the ratio of linear to nonlinear activations. A genetic algorithm is utilized for efficient hyperparameter optimization. To further reduce hardware cost, we developed a framework for 16-bit reduced-precision arithmetic without significantly compromising model performance. Extensive evaluations on standard benchmark datasets demonstrate that our approach delivers competitive accuracy while significantly lowering computational and hardware overhead, making it well-suited for resource-constrained edge environments.
AB - We present a low-overhead reservoir computing framework optimized for edge AI applications by leveraging a combination of several techniques. Specifically, we employ the Simple Cycle Reservoir (SCR) as an alternative to the widely used Echo State Network (ESN), offering a more hardware-efficient design. Our framework evaluates five simplified nonlinear activation functions alongside the conventional hyperbolic tangent function. Additionally, we employ a hyperparameter that enables a tunable trade-off between memory retention and nonlinearity by adjusting the ratio of linear to nonlinear activations. A genetic algorithm is utilized for efficient hyperparameter optimization. To further reduce hardware cost, we developed a framework for 16-bit reduced-precision arithmetic without significantly compromising model performance. Extensive evaluations on standard benchmark datasets demonstrate that our approach delivers competitive accuracy while significantly lowering computational and hardware overhead, making it well-suited for resource-constrained edge environments.
UR - https://www.scopus.com/pages/publications/105029738376
UR - https://www.scopus.com/pages/publications/105029738376#tab=citedBy
U2 - 10.1109/MWSCAS53549.2025.11244461
DO - 10.1109/MWSCAS53549.2025.11244461
M3 - Conference contribution
AN - SCOPUS:105029738376
T3 - Midwest Symposium on Circuits and Systems
SP - 30
EP - 34
BT - 2025 IEEE 68th International Midwest Symposium on Circuits and Systems, MWSCAS 2025
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 68th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2025
Y2 - 10 August 2025 through 13 August 2025
ER -