Exploring wakeup-free instruction scheduling

Jie S. Hu, N. Vijaykrishnan, Mary Jane Irwin

Research output: Contribution to journalConference articlepeer-review

23 Scopus citations


Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free issue queue designs is critically based on their success in predicting the issue latency of an instruction accurately. Consequently, the goal of this paper is to explore the predictability of instruction issue latency under different design constraints and to identify the impediments to performance in such wakeup-free architectures. Our results indicate that structural problems in promoting instructions to the head of the instruction queue from where they are issued in wakeup-free architectures, the limited number of candidate instructions that can be considered for instruction issue, and the resource conflicts due to non-availability of issue ports all have a significant impact in degrading the performance of broadcast free architectures. Based on these observation, we explore an architecture that attempts to overcome the structural limitations by employing traditional selection logic and by using pre-check logic to reduce the impact of resource conflicts while still employing a wakeup-free strategy based on predicted instruction issue latencies. Finally, we improve this technique by limiting the selection logic to a small segment of the issue queue.

Original languageEnglish (US)
Pages (from-to)232-241
Number of pages10
JournalIEEE High-Performance Computer Architecture Symposium Proceedings
StatePublished - 2004
EventProceedings - 10th International Symposium on High Performance Computer Architecture - Madrid, Spain
Duration: Feb 14 2004Feb 18 2004

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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