Extraction of Parasitic Inductances in Three-Phase SiC MOSFET Modules Through Enhanced Two-Port-S-Parameter Measurement

The circuit performance of silicon carbide (SiC) power MOSFET modules are greatly affected by their internal parasitic inductances, which induce adverse effects such as switching oscillations, voltage overshoots, power losses, and electromagnetic interference (EMI) noise. This paper proposes a method for accurately extracting the parasitic inductances of three-phase SiC MOSFET modules using two-port scattering (S) parameter measurement. Similar methods in the existing literature are limited to discrete devices and half-bridge power modules due to the lack of capabilities in measuring coupled inductances on the DC bus between phases. This improved method overcomes the internal complexity of the SiC six-pack power modules and acquires accurate parasitic parameters with minimal steps. The proposed approach is validated through Keysight Advanced Design System (ADS) simulations with official SPICE model parameters. The experiment, conducted on a commercial 1200V SiC six-pack power module, confirms the validity of the approach.