Extraordinary tunnel electroresistance in layer-by-layer engineered van der Waals ferroelectric tunnel junctions

The ability to engineer potential profiles of multilayered materials is critical for designing high-performance tunneling devices such as ferroelectric tunnel junctions (FTJs). FTJs comprise asymmetric electrodes and a ferroelectric spacer, promising semiconductor-platform-compatible logic and memory devices. However, traditional FTJs consist of metal/oxide/metal multilayered structures with unavoidable defects and interfacial trap states, which often cause compromised tunneling electroresistance (TER). Here, we constructed van der Waals (vdW) FTJs by a layered ferroelectric CuInP₂S₆ (CIPS) and graphene. Owing to the gigantic ferroelectric modulation of the chemical potentials in graphene by as large as ∼1 eV, we demonstrated a giant TER of 10⁹. While inserting just a monolayer MoS₂ between CIPS/graphene, the off state is further suppressed, leading to >10¹⁰ TER. Our discovery opens a new solid-state paradigm where potential profiles can be unprecedentedly engineered in a layer-by-layer fashion, fundamentally strengthening the ability to manipulate electrons’ tunneling behaviors and design advanced tunneling devices.