Fabrication of axially-doped silicon nanowire tunnel FETs and characterization of tunneling current

Aaron L. Vallett; Sharis Minassian; Suman Datta; Joan M. Redwing; Theresa S. Mayer

doi:10.1109/DRC.2010.5551962

Fabrication of axially-doped silicon nanowire tunnel FETs and characterization of tunneling current

Aaron L. Vallett, Sharis Minassian, Suman Datta, Joan M. Redwing, Theresa S. Mayer

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Recent interest in low-power electronics has sparked considerable interested in gate-controlled tunneling-based transistors (TFETs), which have demonstrated inverse subthreshold slopes (S) better than the MOSFET limit of 60 mV/dec.¹ While the natural progression of these devices to nanoscale dimensions promises improved performance²³, there is a lack of experimental data regarding the physics of tunneling at reduced dimensions. Here we present a TFET fabricated from an individual axially-doped p ⁺-n-n⁺ Si nanowire in a device layout that enables the study of tunneling physics as the wire dimensions are scaled to the 1D transport regime.

Original language	English (US)
Title of host publication	68th Device Research Conference, DRC 2010
Pages	273-274
Number of pages	2
DOIs	https://doi.org/10.1109/DRC.2010.5551962
State	Published - 2010
Event	68th Device Research Conference, DRC 2010 - Notre Dame, IN, United States Duration: Jun 21 2010 → Jun 23 2010

Publication series

Name	Device Research Conference - Conference Digest, DRC
ISSN (Print)	1548-3770

Other

Other	68th Device Research Conference, DRC 2010
Country/Territory	United States
City	Notre Dame, IN
Period	6/21/10 → 6/23/10

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/DRC.2010.5551962

Cite this

@inproceedings{dc994b5e2c884818a3e6dd0a86ee65a1,

title = "Fabrication of axially-doped silicon nanowire tunnel FETs and characterization of tunneling current",

abstract = "Recent interest in low-power electronics has sparked considerable interested in gate-controlled tunneling-based transistors (TFETs), which have demonstrated inverse subthreshold slopes (S) better than the MOSFET limit of 60 mV/dec.1 While the natural progression of these devices to nanoscale dimensions promises improved performance23, there is a lack of experimental data regarding the physics of tunneling at reduced dimensions. Here we present a TFET fabricated from an individual axially-doped p +-n-n+ Si nanowire in a device layout that enables the study of tunneling physics as the wire dimensions are scaled to the 1D transport regime.",

author = "Vallett, {Aaron L.} and Sharis Minassian and Suman Datta and Redwing, {Joan M.} and Mayer, {Theresa S.}",

year = "2010",

doi = "10.1109/DRC.2010.5551962",

language = "English (US)",

isbn = "9781424478705",

series = "Device Research Conference - Conference Digest, DRC",

pages = "273--274",

booktitle = "68th Device Research Conference, DRC 2010",

note = "68th Device Research Conference, DRC 2010 ; Conference date: 21-06-2010 Through 23-06-2010",

}

Vallett, AL, Minassian, S, Datta, S, Redwing, JM & Mayer, TS 2010, Fabrication of axially-doped silicon nanowire tunnel FETs and characterization of tunneling current. in 68th Device Research Conference, DRC 2010., 5551962, Device Research Conference - Conference Digest, DRC, pp. 273-274, 68th Device Research Conference, DRC 2010, Notre Dame, IN, United States, 6/21/10. https://doi.org/10.1109/DRC.2010.5551962

Fabrication of axially-doped silicon nanowire tunnel FETs and characterization of tunneling current. / Vallett, Aaron L.; Minassian, Sharis; Datta, Suman et al.
68th Device Research Conference, DRC 2010. 2010. p. 273-274 5551962 (Device Research Conference - Conference Digest, DRC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Fabrication of axially-doped silicon nanowire tunnel FETs and characterization of tunneling current

AU - Vallett, Aaron L.

AU - Minassian, Sharis

AU - Datta, Suman

AU - Redwing, Joan M.

AU - Mayer, Theresa S.

PY - 2010

Y1 - 2010

N2 - Recent interest in low-power electronics has sparked considerable interested in gate-controlled tunneling-based transistors (TFETs), which have demonstrated inverse subthreshold slopes (S) better than the MOSFET limit of 60 mV/dec.1 While the natural progression of these devices to nanoscale dimensions promises improved performance23, there is a lack of experimental data regarding the physics of tunneling at reduced dimensions. Here we present a TFET fabricated from an individual axially-doped p +-n-n+ Si nanowire in a device layout that enables the study of tunneling physics as the wire dimensions are scaled to the 1D transport regime.

AB - Recent interest in low-power electronics has sparked considerable interested in gate-controlled tunneling-based transistors (TFETs), which have demonstrated inverse subthreshold slopes (S) better than the MOSFET limit of 60 mV/dec.1 While the natural progression of these devices to nanoscale dimensions promises improved performance23, there is a lack of experimental data regarding the physics of tunneling at reduced dimensions. Here we present a TFET fabricated from an individual axially-doped p +-n-n+ Si nanowire in a device layout that enables the study of tunneling physics as the wire dimensions are scaled to the 1D transport regime.

UR - http://www.scopus.com/inward/record.url?scp=77957562094&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77957562094&partnerID=8YFLogxK

U2 - 10.1109/DRC.2010.5551962

DO - 10.1109/DRC.2010.5551962

M3 - Conference contribution

AN - SCOPUS:77957562094

SN - 9781424478705

T3 - Device Research Conference - Conference Digest, DRC

SP - 273

EP - 274

BT - 68th Device Research Conference, DRC 2010

T2 - 68th Device Research Conference, DRC 2010

Y2 - 21 June 2010 through 23 June 2010

ER -

Fabrication of axially-doped silicon nanowire tunnel FETs and characterization of tunneling current

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