Fast algorithm for performance-oriented Steiner routing

Manjit Borah, Robert Michael Owens, Mary Jane Irwin

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations


We present a routing algorithm which minimizes the Elmore delay to the identified critical sinks while producing routes comparable to the best previously existing Steiner router. Since performance oriented layout generators employ iterative techniques that require a large number of calls to the routing algorithm for layout evaluation, a fast algorithm for routing is desirable. Our algorithm has a fast (O(n2), where n is the number of points) and practical implementation using simple data structures and techniques. Comparisons with other existing algorithms are presented along with results from a performance driven layout generator using our routing algorithm.

Original languageEnglish (US)
Pages (from-to)198-203
Number of pages6
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
StatePublished - Jan 1 1995
EventProceedings of the 5th Great Lakes Symposium on VLSI - Buffalo, NY, USA
Duration: Mar 16 1995Mar 18 1995

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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