Fast compact addition architecture for low power microprocessors and DSP chips

Eric S. Gayles; Robert M. Owens; Mary Jane Irwin

Fast compact addition architecture for low power microprocessors and DSP chips

Eric S. Gayles, Robert M. Owens, Mary Jane Irwin

Research output: Contribution to journal › Conference article › peer-review

Abstract

An addition scheme is presented which has comparable performance to carry-lookahead for the bit precisions required by most microprocessors and DSP chips. The proposed architecture results in adders with regular layout structures, low interconnect complexities, and which occupy little area. Several adders of varying architectures and logic styles were built for comparison with our scheme. Designed with a 3.3 V, 0.5 μm process, at 16-64 bit precisions, our architecture resulted in the lowest energy addition circuits.

Original language	English (US)
Pages (from-to)	41-44
Number of pages	4
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
State	Published - Jan 1 1996
Event	Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA Duration: Sep 23 1996 → Sep 27 1996

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

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abstract = "An addition scheme is presented which has comparable performance to carry-lookahead for the bit precisions required by most microprocessors and DSP chips. The proposed architecture results in adders with regular layout structures, low interconnect complexities, and which occupy little area. Several adders of varying architectures and logic styles were built for comparison with our scheme. Designed with a 3.3 V, 0.5 μm process, at 16-64 bit precisions, our architecture resulted in the lowest energy addition circuits.",

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AU - Owens, Robert M.

AU - Irwin, Mary Jane

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N2 - An addition scheme is presented which has comparable performance to carry-lookahead for the bit precisions required by most microprocessors and DSP chips. The proposed architecture results in adders with regular layout structures, low interconnect complexities, and which occupy little area. Several adders of varying architectures and logic styles were built for comparison with our scheme. Designed with a 3.3 V, 0.5 μm process, at 16-64 bit precisions, our architecture resulted in the lowest energy addition circuits.

AB - An addition scheme is presented which has comparable performance to carry-lookahead for the bit precisions required by most microprocessors and DSP chips. The proposed architecture results in adders with regular layout structures, low interconnect complexities, and which occupy little area. Several adders of varying architectures and logic styles were built for comparison with our scheme. Designed with a 3.3 V, 0.5 μm process, at 16-64 bit precisions, our architecture resulted in the lowest energy addition circuits.

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JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit

Y2 - 23 September 1996 through 27 September 1996

ER -

Fast compact addition architecture for low power microprocessors and DSP chips

Abstract

All Science Journal Classification (ASJC) codes

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