Fast Methods for Switch-Level Verification of MOS Circuits

Douglas S. Reeves; Mary Jane Irwin

doi:10.1109/TCAD.1987.1270320

Fast Methods for Switch-Level Verification of MOS Circuits

Douglas S. Reeves, Mary Jane Irwin

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

Simulation of hardware is a commonly-used method for demonstrating that a circuit design will work for a restricted set of inputs. Verification is a method of proving a circuit design will work for all combinations of input values. Switch-level verification works directly from the circuit netlist. The performance of existing switch-level verifiers has been improved through a combination of techniques. First, efficient methods of finding paths in the switch-graph are developed. Secondly, static analysis of the switch-graph is proposed to accelerate verification of sequential logic. Thirdly, cell replication is exploited in a safe way to make possible the verification of large hierarchical circuit designs. These ideas have been implemented in a program called V, which is part of the Penn State Design System. Experimental results are presented.

Original language	English (US)
Pages (from-to)	766-779
Number of pages	14
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	6
Issue number	5
DOIs	https://doi.org/10.1109/TCAD.1987.1270320
State	Published - Sep 1987

All Science Journal Classification (ASJC) codes

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.1987.1270320

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@article{30347f5c4e6e40d6b30d7845cde197c3,

title = "Fast Methods for Switch-Level Verification of MOS Circuits",

abstract = "Simulation of hardware is a commonly-used method for demonstrating that a circuit design will work for a restricted set of inputs. Verification is a method of proving a circuit design will work for all combinations of input values. Switch-level verification works directly from the circuit netlist. The performance of existing switch-level verifiers has been improved through a combination of techniques. First, efficient methods of finding paths in the switch-graph are developed. Secondly, static analysis of the switch-graph is proposed to accelerate verification of sequential logic. Thirdly, cell replication is exploited in a safe way to make possible the verification of large hierarchical circuit designs. These ideas have been implemented in a program called V, which is part of the Penn State Design System. Experimental results are presented.",

author = "Reeves, {Douglas S.} and Irwin, {Mary Jane}",

year = "1987",

month = sep,

doi = "10.1109/TCAD.1987.1270320",

language = "English (US)",

volume = "6",

pages = "766--779",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - Fast Methods for Switch-Level Verification of MOS Circuits

AU - Reeves, Douglas S.

AU - Irwin, Mary Jane

PY - 1987/9

Y1 - 1987/9

N2 - Simulation of hardware is a commonly-used method for demonstrating that a circuit design will work for a restricted set of inputs. Verification is a method of proving a circuit design will work for all combinations of input values. Switch-level verification works directly from the circuit netlist. The performance of existing switch-level verifiers has been improved through a combination of techniques. First, efficient methods of finding paths in the switch-graph are developed. Secondly, static analysis of the switch-graph is proposed to accelerate verification of sequential logic. Thirdly, cell replication is exploited in a safe way to make possible the verification of large hierarchical circuit designs. These ideas have been implemented in a program called V, which is part of the Penn State Design System. Experimental results are presented.

AB - Simulation of hardware is a commonly-used method for demonstrating that a circuit design will work for a restricted set of inputs. Verification is a method of proving a circuit design will work for all combinations of input values. Switch-level verification works directly from the circuit netlist. The performance of existing switch-level verifiers has been improved through a combination of techniques. First, efficient methods of finding paths in the switch-graph are developed. Secondly, static analysis of the switch-graph is proposed to accelerate verification of sequential logic. Thirdly, cell replication is exploited in a safe way to make possible the verification of large hierarchical circuit designs. These ideas have been implemented in a program called V, which is part of the Penn State Design System. Experimental results are presented.

UR - http://www.scopus.com/inward/record.url?scp=84935502995&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84935502995&partnerID=8YFLogxK

U2 - 10.1109/TCAD.1987.1270320

DO - 10.1109/TCAD.1987.1270320

M3 - Article

AN - SCOPUS:84935502995

SN - 0278-0070

VL - 6

SP - 766

EP - 779

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 5

ER -

Fast Methods for Switch-Level Verification of MOS Circuits

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